Johannes
|
65b951cf82
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# Bank_behav1.wcfg
# lab2CA.runs/.jobs/vrs_config_42.xml
# lab2CA.runs/impl_1/CPU9bits_tb.tcl
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/impl_1/htr.txt
# lab2CA.runs/impl_1/init_design.pb
# lab2CA.runs/impl_1/opt_design.pb
# lab2CA.runs/impl_1/place_design.pb
# lab2CA.runs/impl_1/vivado.jou
# lab2CA.runs/impl_1/vivado.pb
# lab2CA.runs/synth_1/CPU9bits.dcp
# lab2CA.runs/synth_1/CPU9bits.vds
# lab2CA.runs/synth_1/CPU9bits_tb.tcl
# lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
# lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.runs/synth_1/vivado.jou
# lab2CA.runs/synth_1/vivado.pb
# lab2CA.sim/sim_1/behav/xsim/webtalk.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 19:02:52 -04:00 |
|
Johannes
|
be06f4e457
|
Just changes made for simulations
|
2019-03-24 18:55:49 -04:00 |
|
WilliamMiceli
|
4354aebf8c
|
Merged files
|
2019-03-24 17:43:32 -04:00 |
|
jose.rodriguezlabra
|
5a506ba3ab
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 17:33:42 -04:00 |
|
jose.rodriguezlabra
|
efbd7b773b
|
Binary Search completed
It is not fully tested, but it looks pretty good
|
2019-03-24 17:30:27 -04:00 |
|
WilliamMiceli
|
1c44d8d964
|
Added comments to insructions
|
2019-03-24 17:26:44 -04:00 |
|
Johannes
|
033e606d5d
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/dataMemory.v
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
|
2019-03-24 17:08:42 -04:00 |
|
Johannes
|
03df69372a
|
String Compare Working
|
2019-03-24 17:05:09 -04:00 |
|
WilliamMiceli
|
8e72409386
|
Added Bubble Sort instructions and initial data memory
|
2019-03-24 16:54:06 -04:00 |
|
jose.rodriguezlabra
|
335280ccd5
|
Added Binary Search Code
|
2019-03-24 16:35:59 -04:00 |
|
Johannes
|
e8ada91e08
|
BEQ and LD fix
|
2019-03-24 16:05:16 -04:00 |
|
Johannes
|
ee9e420365
|
Added string compare to instruction and data memory
|
2019-03-24 14:14:28 -04:00 |
|
WilliamMiceli
|
ad6765a43a
|
BEQ Opcode fix & other stuffz
|
2019-03-22 19:54:06 -04:00 |
|
Johannes
|
c85ad153dc
|
Tested the instructions using the instruction memory
All of the instructions seem to be working other than beq. I might just be calling it wrong
|
2019-03-20 12:08:24 -04:00 |
|
Johannes
|
e8554a5a9a
|
Minor changes to CPU
|
2019-03-16 14:55:37 -04:00 |
|
Johannes
|
21e846ab62
|
Instruction & Data Memory
|
2019-03-16 14:16:02 -04:00 |
|