Commit Graph
10 Commits
Author SHA1 Message Date
WilliamMiceli cadbc4dd25 Added 9-bit NOT 2019-02-15 15:20:12 -05:00
WilliamMiceli 8b37bee087 Added 9-bit AND module 2019-02-15 15:13:40 -05:00
WilliamMiceli 2a84458894 Added 9-bit adder 2019-02-15 15:07:25 -05:00
WilliamMiceli 81cdf3c62b Added AND gate module 2019-02-15 14:59:38 -05:00
WilliamMiceli 9eec4cdc76 Renamed mux in case we need different kinds later on 2019-02-15 14:56:34 -05:00
WilliamMiceli 3d8ae740f0 Added 1-bit adder 2019-02-15 14:55:11 -05:00
WilliamMiceli 8d78924c04 Added inverter 2019-02-15 14:50:42 -05:00
WilliamMiceli 4421b1a9d6 Reordered into alphabetical order 2019-02-15 14:48:57 -05:00
WilliamMiceli cdb52f35bd Converted MUX to use case statement 2019-02-15 14:46:08 -05:00
WilliamMiceli 337bf5cf13 Removed comment blocks 2019-02-15 14:34:59 -05:00