jose.rodriguezlabra
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ddf47c7eee
|
Tweaked forwarding check. Program 3 works with a few stalls
|
2019-04-12 00:01:27 -04:00 |
|
Johannes
|
a3064a836b
|
Nonsense
|
2019-04-11 19:23:15 -04:00 |
|
WilliamMiceli
|
3129880d50
|
Enabled test data for Program 1
|
2019-04-06 14:18:18 -04:00 |
|
WilliamMiceli
|
9fe8656d21
|
Increased memory size to get rid of unused address ports warning
|
2019-03-29 17:23:00 -04:00 |
|
WilliamMiceli
|
44c057e40d
|
Simplified testbench a little
|
2019-03-29 16:16:11 -04:00 |
|
WilliamMiceli
|
352aeefd1b
|
Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM
|
2019-03-29 16:13:50 -04:00 |
|
WilliamMiceli
|
03eb3f3740
|
Commented out Program 1 test
|
2019-03-29 14:57:29 -04:00 |
|
WilliamMiceli
|
2420d52fc3
|
Added test data for programs to run
|
2019-03-25 16:00:32 -04:00 |
|
WilliamMiceli
|
5353c8c22e
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/CPU9bits.v
# lab2CA.srcs/sources_1/new/dataMemory.v
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2019-03-24 19:31:28 -04:00 |
|
WilliamMiceli
|
7490815502
|
Making fixes to Bubble Sort
|
2019-03-24 19:27:59 -04:00 |
|
Johannes
|
be06f4e457
|
Just changes made for simulations
|
2019-03-24 18:55:49 -04:00 |
|
Johannes
|
033e606d5d
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/dataMemory.v
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
|
2019-03-24 17:08:42 -04:00 |
|
Johannes
|
03df69372a
|
String Compare Working
|
2019-03-24 17:05:09 -04:00 |
|
WilliamMiceli
|
8e72409386
|
Added Bubble Sort instructions and initial data memory
|
2019-03-24 16:54:06 -04:00 |
|
jose.rodriguezlabra
|
335280ccd5
|
Added Binary Search Code
|
2019-03-24 16:35:59 -04:00 |
|
Johannes
|
e8ada91e08
|
BEQ and LD fix
|
2019-03-24 16:05:16 -04:00 |
|
jose.rodriguezlabra
|
27f6d24b88
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
|
2019-03-24 14:17:59 -04:00 |
|
Johannes
|
ee9e420365
|
Added string compare to instruction and data memory
|
2019-03-24 14:14:28 -04:00 |
|
jose.rodriguezlabra
|
bab680ea27
|
Added bank to CPU9bits
|
2019-03-24 12:11:12 -04:00 |
|
Johannes
|
e8554a5a9a
|
Minor changes to CPU
|
2019-03-16 14:55:37 -04:00 |
|
Johannes
|
21e846ab62
|
Instruction & Data Memory
|
2019-03-16 14:16:02 -04:00 |
|