WilliamMiceli
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2a84458894
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Added 9-bit adder
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2019-02-15 15:07:25 -05:00 |
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WilliamMiceli
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81cdf3c62b
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Added AND gate module
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2019-02-15 14:59:38 -05:00 |
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WilliamMiceli
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9eec4cdc76
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Renamed mux in case we need different kinds later on
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2019-02-15 14:56:34 -05:00 |
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WilliamMiceli
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3d8ae740f0
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Added 1-bit adder
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2019-02-15 14:55:11 -05:00 |
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WilliamMiceli
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8d78924c04
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Added inverter
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2019-02-15 14:50:42 -05:00 |
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WilliamMiceli
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4421b1a9d6
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Reordered into alphabetical order
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2019-02-15 14:48:57 -05:00 |
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WilliamMiceli
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cdb52f35bd
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Converted MUX to use case statement
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2019-02-15 14:46:08 -05:00 |
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WilliamMiceli
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337bf5cf13
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Removed comment blocks
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2019-02-15 14:34:59 -05:00 |
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jose.rodriguezlabra
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0b358a6c41
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Set some comments
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2019-02-15 12:38:07 -05:00 |
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jose.rodriguezlabra
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7aa2cfff2a
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Modularized project; mux, clock, and reg done; Progress on RegFile
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2019-02-15 12:24:26 -05:00 |
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