WilliamMiceli
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d8c7031e1b
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Fixed unconnected wires
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2019-03-29 17:21:29 -04:00 |
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WilliamMiceli
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5c165d603a
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Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven
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2019-03-29 16:11:52 -04:00 |
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jose.rodriguezlabra
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3c8147641f
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Added zeroing instr
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2019-03-16 14:34:36 -04:00 |
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jose.rodriguezlabra
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08e3659ba3
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Better Sim
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2019-03-14 14:37:58 -04:00 |
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jose.rodriguezlabra
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11a1d99e92
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Computer works (kinda)
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2019-03-13 12:51:44 -04:00 |
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jose.rodriguezlabra
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026eb65861
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Fixed bugs, finished BEQ, Added Halt
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2019-03-13 11:14:52 -04:00 |
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WilliamMiceli
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76bc5e006e
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Hopefully this is right. Vivado tells me it's fine, then minutes later not...
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2019-03-12 21:21:52 -04:00 |
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WilliamMiceli
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4a462752e9
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Include NOT in the ALU
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2019-03-12 11:23:48 -04:00 |
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WilliamMiceli
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97433c3691
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Shift right arithmetic implemented into ALU
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2019-03-12 11:17:03 -04:00 |
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WilliamMiceli
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fe1abc30c5
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Fixed ALU testbench to 4-bit
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2019-03-12 11:12:39 -04:00 |
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WilliamMiceli
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9ac8963fb0
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ALU now fully has 4-bit opcode
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2019-03-12 11:12:21 -04:00 |
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WilliamMiceli
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9d759edbec
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ALU now has 4 bits of it's own opcode
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2019-03-12 11:07:50 -04:00 |
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WilliamMiceli
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9e9ff7935b
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Renamed shifting for incoming shift_right_arithmetic
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2019-03-12 10:54:45 -04:00 |
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Johannes
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460fc3e4ed
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CPU
LOTS
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2019-03-10 16:32:25 -04:00 |
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WilliamMiceli
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1734d58b47
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Adjusted indentation of testbench code
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2019-02-25 13:27:22 -05:00 |
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WilliamMiceli
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7c83a77713
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Activated all testbenches
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2019-02-25 12:51:34 -05:00 |
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goochey
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54cccd419f
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Lots
Lots
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2019-02-16 17:40:18 -05:00 |
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goochey
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faf9f883dd
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Collaborative - Fixes and Testbenches for Basic Modules so far
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2019-02-16 16:29:12 -05:00 |
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WilliamMiceli
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0b71b05c02
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All current arithmetic and logical operations are now implemented
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2019-02-15 17:51:05 -05:00 |
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WilliamMiceli
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6369170e41
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Comments and slight renames
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2019-02-15 17:49:12 -05:00 |
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WilliamMiceli
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b2dfc05db8
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Renamed some things; adder is now implemented in ALU
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2019-02-15 17:09:44 -05:00 |
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WilliamMiceli
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d6cee0483c
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ALU opcode is different from instruction opcode, so reducing to needed operations only
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2019-02-15 17:02:54 -05:00 |
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WilliamMiceli
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f4c923f60c
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Fixed ALU to use the inputs we're actually going to be giving it
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2019-02-15 16:19:42 -05:00 |
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WilliamMiceli
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365fb5f648
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Moved ALU from simulation sources to design sources
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2019-02-15 16:15:41 -05:00 |
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