Johannes
ee9e420365
Added string compare to instruction and data memory
2019-03-24 14:14:28 -04:00
WilliamMiceli
ad6765a43a
BEQ Opcode fix & other stuffz
2019-03-22 19:54:06 -04:00
Johannes
c85ad153dc
Tested the instructions using the instruction memory
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All of the instructions seem to be working other than beq. I might just be calling it wrong
2019-03-20 12:08:24 -04:00
jose.rodriguezlabra
eeb9c7c318
Tested zero
2019-03-16 14:55:11 -04:00
Johannes
fa5caec5dd
Added memories to the CPU
2019-03-16 14:37:46 -04:00
Johannes
21e846ab62
Instruction & Data Memory
2019-03-16 14:16:02 -04:00
jose.rodriguezlabra
5cbe490aae
Added link instruction
2019-03-16 14:01:32 -04:00
jose.rodriguezlabra
08e3659ba3
Better Sim
2019-03-14 14:37:58 -04:00
jose.rodriguezlabra
11a1d99e92
Computer works (kinda)
2019-03-13 12:51:44 -04:00
jose.rodriguezlabra
026eb65861
Fixed bugs, finished BEQ, Added Halt
2019-03-13 11:14:52 -04:00
Johannes
cb91f6656a
Many Changes
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I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
2019-03-12 21:14:27 -04:00
Johannes
3f01492398
Added SLT
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There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
2019-03-12 19:49:46 -04:00
Johannes
460fc3e4ed
CPU
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LOTS
2019-03-10 16:32:25 -04:00
jose.rodriguezlabra
172238b4e0
Created CPU9bits file
2019-03-10 13:42:30 -04:00
goochey
c047c801aa
Lots of changes
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Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
2019-02-27 12:06:17 -05:00
WilliamMiceli
6900e74405
Miscellaneous
2019-02-21 15:09:00 -05:00
goochey
9ba63880bd
Fetch-Top
2019-02-20 11:40:43 -05:00
goochey
6550b48599
fetch unit test
2019-02-20 11:31:25 -05:00
goochey
54cccd419f
Lots
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Lots
2019-02-16 17:40:18 -05:00
goochey
faf9f883dd
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
jose.rodriguezlabra
0d9cc2b890
Erased weird numbers
2019-02-16 12:50:02 -05:00
jose.rodriguezlabra
bb578e7264
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
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# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/.jobs/vrs_config_1.xml
# lab2CA.runs/.jobs/vrs_config_2.xml
# lab2CA.srcs/sources_1/new/BasicModules.v
2019-02-16 12:33:12 -05:00
WilliamMiceli
456fcf0804
Few renames; added left and right shifts, possibly some other stuff
2019-02-15 17:50:30 -05:00
WilliamMiceli
d1aa8e4ffb
Added outputs to the MUXes for the registers
2019-02-15 17:01:43 -05:00
WilliamMiceli
393f7e7fc5
Added 1-bit and 9-bit OR and NOR modules
2019-02-15 16:16:13 -05:00
WilliamMiceli
68bb7a87e8
Framework of ALU is pretty much done
2019-02-15 15:57:04 -05:00
jose.rodriguezlabra
0b358a6c41
Set some comments
2019-02-15 12:38:07 -05:00
jose.rodriguezlabra
7aa2cfff2a
Modularized project; mux, clock, and reg done; Progress on RegFile
2019-02-15 12:24:26 -05:00
goochey
1691adf1b5
fetch unit
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A little fetch unit
2019-02-15 11:20:14 -05:00
jose.rodriguezlabra
b93a3779cc
First upload
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CODE HERE!!!!!!!!!!
2019-02-08 18:18:54 -05:00
