fa5e1d2739
Idek what ive changed its been so long
2019-04-11 21:54:34 -04:00
a3064a836b
Nonsense
2019-04-11 19:23:15 -04:00
bc9c02322c
Added forwarding
2019-04-11 18:36:00 -04:00
42d2bf2d80
Fixed pip enables, fixed Nop/Halt
2019-04-11 17:32:17 -04:00
eaec5f0883
Vivado stuff
2019-04-10 12:51:15 -04:00
616dac4d29
Changes
2019-04-06 17:54:50 -04:00
e6cb8e536b
Added Pipeline
2019-04-06 17:51:44 -04:00
e937485bd4
Vivado stuff
2019-04-06 17:44:26 -04:00
b3e2adb097
Updated simulation
2019-04-06 16:05:47 -04:00
de8740a231
Vivado runs/sim
2019-04-06 14:16:26 -04:00
78f481f724
Vivado stuff
2019-03-29 17:29:24 -04:00
5353c8c22e
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/CPU9bits.v
# lab2CA.srcs/sources_1/new/dataMemory.v
2019-03-24 19:31:28 -04:00
7490815502
Making fixes to Bubble Sort
2019-03-24 19:27:59 -04:00
65b951cf82
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# Bank_behav1.wcfg
# lab2CA.runs/.jobs/vrs_config_42.xml
# lab2CA.runs/impl_1/CPU9bits_tb.tcl
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/impl_1/htr.txt
# lab2CA.runs/impl_1/init_design.pb
# lab2CA.runs/impl_1/opt_design.pb
# lab2CA.runs/impl_1/place_design.pb
# lab2CA.runs/impl_1/vivado.jou
# lab2CA.runs/impl_1/vivado.pb
# lab2CA.runs/synth_1/CPU9bits.dcp
# lab2CA.runs/synth_1/CPU9bits.vds
# lab2CA.runs/synth_1/CPU9bits_tb.tcl
# lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
# lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.runs/synth_1/vivado.jou
# lab2CA.runs/synth_1/vivado.pb
# lab2CA.sim/sim_1/behav/xsim/webtalk.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
2019-03-24 19:02:52 -04:00
be06f4e457
Just changes made for simulations
2019-03-24 18:55:49 -04:00
4354aebf8c
Merged files
2019-03-24 17:43:32 -04:00
681c506eec
Renamed signals on simulation waveforms
2019-03-24 17:42:38 -04:00
033e606d5d
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/dataMemory.v
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
2019-03-24 17:08:42 -04:00
03df69372a
String Compare Working
2019-03-24 17:05:09 -04:00
335280ccd5
Added Binary Search Code
2019-03-24 16:35:59 -04:00
9a2e84bda6
metadata
2019-03-24 16:09:40 -04:00
e8ada91e08
BEQ and LD fix
2019-03-24 16:05:16 -04:00
27f6d24b88
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
2019-03-24 14:17:59 -04:00
ee9e420365
Added string compare to instruction and data memory
2019-03-24 14:14:28 -04:00
bab680ea27
Added bank to CPU9bits
2019-03-24 12:11:12 -04:00
ad6765a43a
BEQ Opcode fix & other stuffz
2019-03-22 19:54:06 -04:00
c85ad153dc
Tested the instructions using the instruction memory
...
All of the instructions seem to be working other than beq. I might just be calling it wrong
2019-03-20 12:08:24 -04:00
eeb9c7c318
Tested zero
2019-03-16 14:55:11 -04:00
fa5caec5dd
Added memories to the CPU
2019-03-16 14:37:46 -04:00
21e846ab62
Instruction & Data Memory
2019-03-16 14:16:02 -04:00
dfd8753a62
Implemented SEs
2019-03-16 14:09:53 -04:00
5cbe490aae
Added link instruction
2019-03-16 14:01:32 -04:00
08e3659ba3
Better Sim
2019-03-14 14:37:58 -04:00
11a1d99e92
Computer works (kinda)
2019-03-13 12:51:44 -04:00
cb91f6656a
Many Changes
...
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
2019-03-12 21:14:27 -04:00
3f01492398
Added SLT
...
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
2019-03-12 19:49:46 -04:00
8a903ebcfd
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# regFile_tb_behav.wcfg
2019-03-10 13:00:12 -04:00
4c19de70bc
Metadatapush
2019-03-10 12:59:09 -04:00
c047c801aa
Lots of changes
...
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
2019-02-27 12:06:17 -05:00
6900e74405
Miscellaneous
2019-02-21 15:09:00 -05:00
6550b48599
fetch unit test
2019-02-20 11:31:25 -05:00
54cccd419f
Lots
...
Lots
2019-02-16 17:40:18 -05:00
faf9f883dd
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
0b358a6c41
Set some comments
2019-02-15 12:38:07 -05:00
Johannes
jose.rodriguezlabra
WilliamMiceli