William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
139 Commits 1 Branch 0 Tags
445f5ce83005aaa73938b3f1f2fa62b415742fdc
Commit Graph

112 Commits

Author SHA1 Message Date
WilliamMiceli
445f5ce830 Removed CLK, as it is not needed 2019-03-29 16:16:36 -04:00
WilliamMiceli
44c057e40d Simplified testbench a little 2019-03-29 16:16:11 -04:00
WilliamMiceli
20def71bb1 Removed references to CLK, as not needed; simplified testbench a little 2019-03-29 16:15:47 -04:00
WilliamMiceli
352aeefd1b Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM 2019-03-29 16:13:50 -04:00
WilliamMiceli
5bd244f9ba Now Asynchronous and recognized by Vivado as RTL_ROM 2019-03-29 16:13:07 -04:00
WilliamMiceli
5c165d603a Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven 2019-03-29 16:11:52 -04:00
WilliamMiceli
03eb3f3740 Commented out Program 1 test 2019-03-29 14:57:29 -04:00
WilliamMiceli
97fcfb7ef1 Fixed equation solver instructions 2019-03-25 17:08:22 -04:00
WilliamMiceli
2420d52fc3 Added test data for programs to run 2019-03-25 16:00:32 -04:00
WilliamMiceli
5353c8c22e Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/CPU9bits.v
#	lab2CA.srcs/sources_1/new/dataMemory.v
 2019-03-24 19:31:28 -04:00
WilliamMiceli
7490815502 Making fixes to Bubble Sort 2019-03-24 19:27:59 -04:00
Johannes
65b951cf82 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	Bank_behav1.wcfg
#	lab2CA.runs/.jobs/vrs_config_42.xml
#	lab2CA.runs/impl_1/CPU9bits_tb.tcl
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/impl_1/htr.txt
#	lab2CA.runs/impl_1/init_design.pb
#	lab2CA.runs/impl_1/opt_design.pb
#	lab2CA.runs/impl_1/place_design.pb
#	lab2CA.runs/impl_1/vivado.jou
#	lab2CA.runs/impl_1/vivado.pb
#	lab2CA.runs/synth_1/CPU9bits.dcp
#	lab2CA.runs/synth_1/CPU9bits.vds
#	lab2CA.runs/synth_1/CPU9bits_tb.tcl
#	lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
#	lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.runs/synth_1/vivado.jou
#	lab2CA.runs/synth_1/vivado.pb
#	lab2CA.sim/sim_1/behav/xsim/webtalk.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 19:02:52 -04:00
Johannes
be06f4e457 Just changes made for simulations 2019-03-24 18:55:49 -04:00
WilliamMiceli
4354aebf8c Merged files 2019-03-24 17:43:32 -04:00
jose.rodriguezlabra
5a506ba3ab Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 17:33:42 -04:00
jose.rodriguezlabra
efbd7b773b Binary Search completed 
It is not fully tested, but it looks pretty good
 2019-03-24 17:30:27 -04:00
WilliamMiceli
1c44d8d964 Added comments to insructions 2019-03-24 17:26:44 -04:00
Johannes
033e606d5d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/dataMemory.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 17:08:42 -04:00
Johannes
03df69372a String Compare Working 2019-03-24 17:05:09 -04:00
WilliamMiceli
8e72409386 Added Bubble Sort instructions and initial data memory 2019-03-24 16:54:06 -04:00
jose.rodriguezlabra
335280ccd5 Added Binary Search Code 2019-03-24 16:35:59 -04:00
Johannes
ace0eca65a Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.xpr
 2019-03-24 16:06:29 -04:00
Johannes
e8ada91e08 BEQ and LD fix 2019-03-24 16:05:16 -04:00
jose.rodriguezlabra
ce2410e26c little things 2019-03-24 16:04:55 -04:00
jose.rodriguezlabra
27f6d24b88 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 14:17:59 -04:00
jose.rodriguezlabra
94f0267a13 stuff 2019-03-24 14:16:03 -04:00
Johannes
ee9e420365 Added string compare to instruction and data memory 2019-03-24 14:14:28 -04:00
jose.rodriguezlabra
bab680ea27 Added bank to CPU9bits 2019-03-24 12:11:12 -04:00
WilliamMiceli
ad6765a43a BEQ Opcode fix & other stuffz 2019-03-22 19:54:06 -04:00
Johannes
c85ad153dc Tested the instructions using the instruction memory 
All of the instructions seem to be working other than beq. I might just be calling it wrong
 2019-03-20 12:08:24 -04:00
Johannes
0f55e62a2e Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-03-16 14:56:00 -04:00
Johannes
e8554a5a9a Minor changes to CPU 2019-03-16 14:55:37 -04:00
jose.rodriguezlabra
eeb9c7c318 Tested zero 2019-03-16 14:55:11 -04:00
Johannes
fa5caec5dd Added memories to the CPU 2019-03-16 14:37:46 -04:00
jose.rodriguezlabra
3c8147641f Added zeroing instr 2019-03-16 14:34:36 -04:00
Johannes
21e846ab62 Instruction & Data Memory 2019-03-16 14:16:02 -04:00
jose.rodriguezlabra
dfd8753a62 Implemented SEs 2019-03-16 14:09:53 -04:00
jose.rodriguezlabra
5cbe490aae Added link instruction 2019-03-16 14:01:32 -04:00
WilliamMiceli
934c73e899 Small formatting change 2019-03-16 13:44:44 -04:00
WilliamMiceli
b621f5a46b Added sign extension for 3 bits up to 8 bits 2019-03-16 13:23:22 -04:00
WilliamMiceli
ef8b9c92e5 Made testbench 2019-03-16 13:02:29 -04:00
WilliamMiceli
c988ddb899 Fixed 2 bit module 2019-03-16 13:02:18 -04:00
WilliamMiceli
19ac8e130c Added sign extension for 2 bits into 9 bits, just to test first 2019-03-16 12:55:57 -04:00
jose.rodriguezlabra
08e3659ba3 Better Sim 2019-03-14 14:37:58 -04:00
jose.rodriguezlabra
11a1d99e92 Computer works (kinda) 2019-03-13 12:51:44 -04:00
jose.rodriguezlabra
026eb65861 Fixed bugs, finished BEQ, Added Halt 2019-03-13 11:14:52 -04:00
WilliamMiceli
1e0e2bbf31 Jose's awesome way to test zero structurally! 2019-03-12 23:01:18 -04:00
Johannes
a9a4e81c6c Removed my behavioral slt 2019-03-12 21:33:24 -04:00
Johannes
735970454a My set less than was behavioral which is a no no 
# Conflicts:
#	lab2CA.srcs/sources_1/new/ALU.v
 2019-03-12 21:30:00 -04:00
WilliamMiceli
76bc5e006e Hopefully this is right. Vivado tells me it's fine, then minutes later not... 2019-03-12 21:21:52 -04:00