 jose.rodriguezlabra
|
d60aa9d1e8
|
more stuff
|
2019-02-16 12:42:09 -05:00 |
|
|
jose.rodriguezlabra
|
22bf2728ba
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.srcs/sources_1/new/BasicModules.v
|
2019-02-16 12:39:15 -05:00 |
|
|
jose.rodriguezlabra
|
9aa7a5f0b0
|
stuff
|
2019-02-16 12:37:12 -05:00 |
|
 goochey
|
b2eb0da26c
|
Fetch Unit Again
I think I did it wrong
|
2019-02-16 12:36:26 -05:00 |
|
|
jose.rodriguezlabra
|
bb578e7264
|
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/.jobs/vrs_config_1.xml
# lab2CA.runs/.jobs/vrs_config_2.xml
# lab2CA.srcs/sources_1/new/BasicModules.v
|
2019-02-16 12:33:12 -05:00 |
|
|
goochey
|
34376a588e
|
fetch unit
Should be done. also added 2 to 1 mux
|
2019-02-16 12:28:49 -05:00 |
|
 WilliamMiceli
|
5458d27391
|
Vivado data stuff
|
2019-02-15 17:51:58 -05:00 |
|
|
WilliamMiceli
|
0b71b05c02
|
All current arithmetic and logical operations are now implemented
|
2019-02-15 17:51:05 -05:00 |
|
|
WilliamMiceli
|
456fcf0804
|
Few renames; added left and right shifts, possibly some other stuff
|
2019-02-15 17:50:30 -05:00 |
|
|
WilliamMiceli
|
6369170e41
|
Comments and slight renames
|
2019-02-15 17:49:12 -05:00 |
|
|
WilliamMiceli
|
32faa621d6
|
Added Two's Compliment module
|
2019-02-15 17:18:54 -05:00 |
|
|
WilliamMiceli
|
b2dfc05db8
|
Renamed some things; adder is now implemented in ALU
|
2019-02-15 17:09:44 -05:00 |
|
|
WilliamMiceli
|
d6cee0483c
|
ALU opcode is different from instruction opcode, so reducing to needed operations only
|
2019-02-15 17:02:54 -05:00 |
|
|
WilliamMiceli
|
582c80998e
|
Added 8:1 MUX
|
2019-02-15 17:02:11 -05:00 |
|
|
WilliamMiceli
|
d1aa8e4ffb
|
Added outputs to the MUXes for the registers
|
2019-02-15 17:01:43 -05:00 |
|
|
WilliamMiceli
|
f4c923f60c
|
Fixed ALU to use the inputs we're actually going to be giving it
|
2019-02-15 16:19:42 -05:00 |
|
|
WilliamMiceli
|
393f7e7fc5
|
Added 1-bit and 9-bit OR and NOR modules
|
2019-02-15 16:16:13 -05:00 |
|
|
WilliamMiceli
|
365fb5f648
|
Moved ALU from simulation sources to design sources
|
2019-02-15 16:15:41 -05:00 |
|
|
WilliamMiceli
|
10e9e0b359
|
Added 1-bit NOR
|
2019-02-15 16:05:07 -05:00 |
|
|
WilliamMiceli
|
68bb7a87e8
|
Framework of ALU is pretty much done
|
2019-02-15 15:57:04 -05:00 |
|
|
WilliamMiceli
|
9628b971d7
|
Fixed a few syntax errors
|
2019-02-15 15:40:20 -05:00 |
|
|
WilliamMiceli
|
fd22d5c7e6
|
Added 16:1 MUX for our ALU
|
2019-02-15 15:33:02 -05:00 |
|
|
WilliamMiceli
|
cadbc4dd25
|
Added 9-bit NOT
|
2019-02-15 15:20:12 -05:00 |
|
|
WilliamMiceli
|
8b37bee087
|
Added 9-bit AND module
|
2019-02-15 15:13:40 -05:00 |
|
|
WilliamMiceli
|
2a84458894
|
Added 9-bit adder
|
2019-02-15 15:07:25 -05:00 |
|
|
WilliamMiceli
|
81cdf3c62b
|
Added AND gate module
|
2019-02-15 14:59:38 -05:00 |
|
|
WilliamMiceli
|
9eec4cdc76
|
Renamed mux in case we need different kinds later on
|
2019-02-15 14:56:34 -05:00 |
|
|
WilliamMiceli
|
3d8ae740f0
|
Added 1-bit adder
|
2019-02-15 14:55:11 -05:00 |
|
|
WilliamMiceli
|
8d78924c04
|
Added inverter
|
2019-02-15 14:50:42 -05:00 |
|
|
WilliamMiceli
|
4421b1a9d6
|
Reordered into alphabetical order
|
2019-02-15 14:48:57 -05:00 |
|
|
WilliamMiceli
|
cdb52f35bd
|
Converted MUX to use case statement
|
2019-02-15 14:46:08 -05:00 |
|
|
WilliamMiceli
|
337bf5cf13
|
Removed comment blocks
|
2019-02-15 14:34:59 -05:00 |
|
|
jose.rodriguezlabra
|
0b358a6c41
|
Set some comments
|
2019-02-15 12:38:07 -05:00 |
|
|
jose.rodriguezlabra
|
7aa2cfff2a
|
Modularized project; mux, clock, and reg done; Progress on RegFile
|
2019-02-15 12:24:26 -05:00 |
|
|
jose.rodriguezlabra
|
d147e12073
|
Forgot to stage this file
|
2019-02-15 11:53:54 -05:00 |
|
|
jose.rodriguezlabra
|
3378e5bfd8
|
Merge resolve?
|
2019-02-15 11:53:29 -05:00 |
|
|
goochey
|
1691adf1b5
|
fetch unit
A little fetch unit
|
2019-02-15 11:20:14 -05:00 |
|
 jose.rodriguezlabra
|
b93a3779cc
|
First upload
CODE HERE!!!!!!!!!!
|
2019-02-08 18:18:54 -05:00 |
|
 William Miceli
|
0b9b2e00a5
|
Initial commit, gitignore
|
2019-02-08 18:10:13 -05:00 |
|