WilliamMiceli
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d6cee0483c
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ALU opcode is different from instruction opcode, so reducing to needed operations only
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2019-02-15 17:02:54 -05:00 |
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WilliamMiceli
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582c80998e
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Added 8:1 MUX
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2019-02-15 17:02:11 -05:00 |
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WilliamMiceli
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d1aa8e4ffb
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Added outputs to the MUXes for the registers
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2019-02-15 17:01:43 -05:00 |
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WilliamMiceli
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f4c923f60c
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Fixed ALU to use the inputs we're actually going to be giving it
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2019-02-15 16:19:42 -05:00 |
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WilliamMiceli
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393f7e7fc5
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Added 1-bit and 9-bit OR and NOR modules
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2019-02-15 16:16:13 -05:00 |
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WilliamMiceli
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365fb5f648
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Moved ALU from simulation sources to design sources
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2019-02-15 16:15:41 -05:00 |
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WilliamMiceli
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10e9e0b359
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Added 1-bit NOR
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2019-02-15 16:05:07 -05:00 |
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WilliamMiceli
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68bb7a87e8
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Framework of ALU is pretty much done
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2019-02-15 15:57:04 -05:00 |
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WilliamMiceli
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9628b971d7
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Fixed a few syntax errors
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2019-02-15 15:40:20 -05:00 |
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WilliamMiceli
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fd22d5c7e6
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Added 16:1 MUX for our ALU
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2019-02-15 15:33:02 -05:00 |
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WilliamMiceli
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cadbc4dd25
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Added 9-bit NOT
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2019-02-15 15:20:12 -05:00 |
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WilliamMiceli
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8b37bee087
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Added 9-bit AND module
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2019-02-15 15:13:40 -05:00 |
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WilliamMiceli
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2a84458894
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Added 9-bit adder
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2019-02-15 15:07:25 -05:00 |
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WilliamMiceli
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81cdf3c62b
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Added AND gate module
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2019-02-15 14:59:38 -05:00 |
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WilliamMiceli
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9eec4cdc76
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Renamed mux in case we need different kinds later on
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2019-02-15 14:56:34 -05:00 |
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WilliamMiceli
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3d8ae740f0
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Added 1-bit adder
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2019-02-15 14:55:11 -05:00 |
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WilliamMiceli
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8d78924c04
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Added inverter
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2019-02-15 14:50:42 -05:00 |
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WilliamMiceli
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4421b1a9d6
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Reordered into alphabetical order
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2019-02-15 14:48:57 -05:00 |
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WilliamMiceli
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cdb52f35bd
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Converted MUX to use case statement
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2019-02-15 14:46:08 -05:00 |
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WilliamMiceli
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337bf5cf13
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Removed comment blocks
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2019-02-15 14:34:59 -05:00 |
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jose.rodriguezlabra
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7aa2cfff2a
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Modularized project; mux, clock, and reg done; Progress on RegFile
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2019-02-15 12:24:26 -05:00 |
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jose.rodriguezlabra
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d147e12073
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Forgot to stage this file
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2019-02-15 11:53:54 -05:00 |
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jose.rodriguezlabra
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3378e5bfd8
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Merge resolve?
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2019-02-15 11:53:29 -05:00 |
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goochey
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1691adf1b5
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fetch unit
A little fetch unit
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2019-02-15 11:20:14 -05:00 |
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jose.rodriguezlabra
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b93a3779cc
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First upload
CODE HERE!!!!!!!!!!
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2019-02-08 18:18:54 -05:00 |
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William Miceli
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0b9b2e00a5
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Initial commit, gitignore
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2019-02-08 18:10:13 -05:00 |
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