2746d6d49c
Added pipeline registers
2019-04-06 13:13:47 -04:00
5353c8c22e
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/CPU9bits.v
# lab2CA.srcs/sources_1/new/dataMemory.v
2019-03-24 19:31:28 -04:00
7490815502
Making fixes to Bubble Sort
2019-03-24 19:27:59 -04:00
65b951cf82
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# Bank_behav1.wcfg
# lab2CA.runs/.jobs/vrs_config_42.xml
# lab2CA.runs/impl_1/CPU9bits_tb.tcl
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/impl_1/htr.txt
# lab2CA.runs/impl_1/init_design.pb
# lab2CA.runs/impl_1/opt_design.pb
# lab2CA.runs/impl_1/place_design.pb
# lab2CA.runs/impl_1/vivado.jou
# lab2CA.runs/impl_1/vivado.pb
# lab2CA.runs/synth_1/CPU9bits.dcp
# lab2CA.runs/synth_1/CPU9bits.vds
# lab2CA.runs/synth_1/CPU9bits_tb.tcl
# lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
# lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.runs/synth_1/vivado.jou
# lab2CA.runs/synth_1/vivado.pb
# lab2CA.sim/sim_1/behav/xsim/webtalk.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
# lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
2019-03-24 19:02:52 -04:00
be06f4e457
Just changes made for simulations
2019-03-24 18:55:49 -04:00
4354aebf8c
Merged files
2019-03-24 17:43:32 -04:00
5a506ba3ab
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
2019-03-24 17:33:42 -04:00
efbd7b773b
Binary Search completed
...
It is not fully tested, but it looks pretty good
2019-03-24 17:30:27 -04:00
1c44d8d964
Added comments to insructions
2019-03-24 17:26:44 -04:00
033e606d5d
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/dataMemory.v
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
2019-03-24 17:08:42 -04:00
03df69372a
String Compare Working
2019-03-24 17:05:09 -04:00
8e72409386
Added Bubble Sort instructions and initial data memory
2019-03-24 16:54:06 -04:00
335280ccd5
Added Binary Search Code
2019-03-24 16:35:59 -04:00
ace0eca65a
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.xpr
2019-03-24 16:06:29 -04:00
e8ada91e08
BEQ and LD fix
2019-03-24 16:05:16 -04:00
ce2410e26c
little things
2019-03-24 16:04:55 -04:00
27f6d24b88
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
2019-03-24 14:17:59 -04:00
94f0267a13
stuff
2019-03-24 14:16:03 -04:00
ee9e420365
Added string compare to instruction and data memory
2019-03-24 14:14:28 -04:00
bab680ea27
Added bank to CPU9bits
2019-03-24 12:11:12 -04:00
ad6765a43a
BEQ Opcode fix & other stuffz
2019-03-22 19:54:06 -04:00
c85ad153dc
Tested the instructions using the instruction memory
...
All of the instructions seem to be working other than beq. I might just be calling it wrong
2019-03-20 12:08:24 -04:00
0f55e62a2e
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-16 14:56:00 -04:00
e8554a5a9a
Minor changes to CPU
2019-03-16 14:55:37 -04:00
eeb9c7c318
Tested zero
2019-03-16 14:55:11 -04:00
fa5caec5dd
Added memories to the CPU
2019-03-16 14:37:46 -04:00
3c8147641f
Added zeroing instr
2019-03-16 14:34:36 -04:00
21e846ab62
Instruction & Data Memory
2019-03-16 14:16:02 -04:00
dfd8753a62
Implemented SEs
2019-03-16 14:09:53 -04:00
5cbe490aae
Added link instruction
2019-03-16 14:01:32 -04:00
934c73e899
Small formatting change
2019-03-16 13:44:44 -04:00
b621f5a46b
Added sign extension for 3 bits up to 8 bits
2019-03-16 13:23:22 -04:00
ef8b9c92e5
Made testbench
2019-03-16 13:02:29 -04:00
c988ddb899
Fixed 2 bit module
2019-03-16 13:02:18 -04:00
19ac8e130c
Added sign extension for 2 bits into 9 bits, just to test first
2019-03-16 12:55:57 -04:00
08e3659ba3
Better Sim
2019-03-14 14:37:58 -04:00
11a1d99e92
Computer works (kinda)
2019-03-13 12:51:44 -04:00
026eb65861
Fixed bugs, finished BEQ, Added Halt
2019-03-13 11:14:52 -04:00
1e0e2bbf31
Jose's awesome way to test zero structurally!
2019-03-12 23:01:18 -04:00
a9a4e81c6c
Removed my behavioral slt
2019-03-12 21:33:24 -04:00
735970454a
My set less than was behavioral which is a no no
...
# Conflicts:
# lab2CA.srcs/sources_1/new/ALU.v
2019-03-12 21:30:00 -04:00
76bc5e006e
Hopefully this is right. Vivado tells me it's fine, then minutes later not...
2019-03-12 21:21:52 -04:00
cb91f6656a
Many Changes
...
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
2019-03-12 21:14:27 -04:00
3f01492398
Added SLT
...
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
2019-03-12 19:49:46 -04:00
4a462752e9
Include NOT in the ALU
2019-03-12 11:23:48 -04:00
97433c3691
Shift right arithmetic implemented into ALU
2019-03-12 11:17:03 -04:00
fe1abc30c5
Fixed ALU testbench to 4-bit
2019-03-12 11:12:39 -04:00
9ac8963fb0
ALU now fully has 4-bit opcode
2019-03-12 11:12:21 -04:00
1c5e79c1ec
Made 16:1 MUX for ALU's 4-bit opcode
2019-03-12 11:08:22 -04:00
9d759edbec
ALU now has 4 bits of it's own opcode
2019-03-12 11:07:50 -04:00
Johannes
WilliamMiceli
jose.rodriguezlabra