William/WMU-ECE-3570-Lab
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Author SHA1 Message Date
jose.rodriguezlabra 5a506ba3ab Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 17:33:42 -04:00
jose.rodriguezlabra efbd7b773b Binary Search completed 
It is not fully tested, but it looks pretty good
 2019-03-24 17:30:27 -04:00
WilliamMiceli 1c44d8d964 Added comments to insructions 2019-03-24 17:26:44 -04:00
Johannes 033e606d5d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/dataMemory.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 17:08:42 -04:00
Johannes 03df69372a String Compare Working 2019-03-24 17:05:09 -04:00
WilliamMiceli 8e72409386 Added Bubble Sort instructions and initial data memory 2019-03-24 16:54:06 -04:00
jose.rodriguezlabra 335280ccd5 Added Binary Search Code 2019-03-24 16:35:59 -04:00
WilliamMiceli a978e1fbc6 Revert file 2019-03-24 16:11:31 -04:00
Johannes 9a2e84bda6 metadata 2019-03-24 16:09:40 -04:00
Johannes ace0eca65a Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.xpr
 2019-03-24 16:06:29 -04:00
jose.rodriguezlabra eac5d71dd6 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
 2019-03-24 16:05:40 -04:00
Johannes e8ada91e08 BEQ and LD fix 2019-03-24 16:05:16 -04:00
jose.rodriguezlabra ce2410e26c little things 2019-03-24 16:04:55 -04:00
WilliamMiceli f17a0c8954 Replaced missing simulation configuration file 2019-03-24 15:52:26 -04:00
jose.rodriguezlabra 27f6d24b88 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 14:17:59 -04:00
jose.rodriguezlabra 94f0267a13 stuff 2019-03-24 14:16:03 -04:00
Johannes ee9e420365 Added string compare to instruction and data memory 2019-03-24 14:14:28 -04:00
Johannes 395a8b6f8f Revert "metadata" 
This reverts commit 191ca46f2d.
 2019-03-24 13:01:08 -04:00
Johannes 2af68f2731 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-03-24 12:59:29 -04:00
Johannes a57af01a47 Revert "Changed datamemory" 
This reverts commit 90d9d69885.
 2019-03-24 12:49:08 -04:00
Johannes 90d9d69885 Changed datamemory 2019-03-24 12:47:18 -04:00
jose.rodriguezlabra bab680ea27 Added bank to CPU9bits 2019-03-24 12:11:12 -04:00
jose.rodriguezlabra 191ca46f2d metadata 2019-03-24 10:07:28 -04:00
WilliamMiceli ad6765a43a BEQ Opcode fix & other stuffz 2019-03-22 19:54:06 -04:00
Johannes c85ad153dc Tested the instructions using the instruction memory 
All of the instructions seem to be working other than beq. I might just be calling it wrong
 2019-03-20 12:08:24 -04:00
Johannes 0f55e62a2e Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-03-16 14:56:00 -04:00
Johannes e8554a5a9a Minor changes to CPU 2019-03-16 14:55:37 -04:00
jose.rodriguezlabra eeb9c7c318 Tested zero 2019-03-16 14:55:11 -04:00
Johannes fa5caec5dd Added memories to the CPU 2019-03-16 14:37:46 -04:00
jose.rodriguezlabra 3c8147641f Added zeroing instr 2019-03-16 14:34:36 -04:00
Johannes 21e846ab62 Instruction & Data Memory 2019-03-16 14:16:02 -04:00
jose.rodriguezlabra dfd8753a62 Implemented SEs 2019-03-16 14:09:53 -04:00
jose.rodriguezlabra 5cbe490aae Added link instruction 2019-03-16 14:01:32 -04:00
WilliamMiceli 934c73e899 Small formatting change 2019-03-16 13:44:44 -04:00
WilliamMiceli b621f5a46b Added sign extension for 3 bits up to 8 bits 2019-03-16 13:23:22 -04:00
WilliamMiceli ef8b9c92e5 Made testbench 2019-03-16 13:02:29 -04:00
WilliamMiceli c988ddb899 Fixed 2 bit module 2019-03-16 13:02:18 -04:00
WilliamMiceli 19ac8e130c Added sign extension for 2 bits into 9 bits, just to test first 2019-03-16 12:55:57 -04:00
jose.rodriguezlabra 08e3659ba3 Better Sim 2019-03-14 14:37:58 -04:00
jose.rodriguezlabra 11a1d99e92 Computer works (kinda) 2019-03-13 12:51:44 -04:00
jose.rodriguezlabra 026eb65861 Fixed bugs, finished BEQ, Added Halt 2019-03-13 11:14:52 -04:00
jose.rodriguezlabra 911d8e31cc Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
 2019-03-13 09:01:33 -04:00
jose.rodriguezlabra f6772daf04 Worthless metadata 2019-03-13 09:00:40 -04:00
WilliamMiceli 047efb7f1f More Vivado stuff 2019-03-12 23:04:47 -04:00
WilliamMiceli 1e0e2bbf31 Jose's awesome way to test zero structurally! 2019-03-12 23:01:18 -04:00
WilliamMiceli 1efd958593 Vivado stuff 2019-03-12 22:56:03 -04:00
WilliamMiceli dbdfc2cfc6 Updated README 2019-03-12 21:53:50 -04:00
Johannes a9a4e81c6c Removed my behavioral slt 2019-03-12 21:33:24 -04:00
Johannes 735970454a My set less than was behavioral which is a no no 
# Conflicts:
#	lab2CA.srcs/sources_1/new/ALU.v
 2019-03-12 21:30:00 -04:00
WilliamMiceli 76bc5e006e Hopefully this is right. Vivado tells me it's fine, then minutes later not... 2019-03-12 21:21:52 -04:00