WilliamMiceli
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7490815502
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Making fixes to Bubble Sort
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2019-03-24 19:27:59 -04:00 |
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WilliamMiceli
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4354aebf8c
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Merged files
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2019-03-24 17:43:32 -04:00 |
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WilliamMiceli
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681c506eec
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Renamed signals on simulation waveforms
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2019-03-24 17:42:38 -04:00 |
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jose.rodriguezlabra
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5a506ba3ab
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 17:33:42 -04:00 |
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jose.rodriguezlabra
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efbd7b773b
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Binary Search completed
It is not fully tested, but it looks pretty good
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2019-03-24 17:30:27 -04:00 |
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WilliamMiceli
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1c44d8d964
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Added comments to insructions
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2019-03-24 17:26:44 -04:00 |
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Johannes
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033e606d5d
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/dataMemory.v
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 17:08:42 -04:00 |
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Johannes
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03df69372a
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String Compare Working
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2019-03-24 17:05:09 -04:00 |
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WilliamMiceli
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8e72409386
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Added Bubble Sort instructions and initial data memory
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2019-03-24 16:54:06 -04:00 |
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jose.rodriguezlabra
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335280ccd5
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Added Binary Search Code
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2019-03-24 16:35:59 -04:00 |
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WilliamMiceli
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a978e1fbc6
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Revert file
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2019-03-24 16:11:31 -04:00 |
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Johannes
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9a2e84bda6
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metadata
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2019-03-24 16:09:40 -04:00 |
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Johannes
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ace0eca65a
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.xpr
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2019-03-24 16:06:29 -04:00 |
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jose.rodriguezlabra
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eac5d71dd6
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
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2019-03-24 16:05:40 -04:00 |
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Johannes
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e8ada91e08
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BEQ and LD fix
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2019-03-24 16:05:16 -04:00 |
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jose.rodriguezlabra
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ce2410e26c
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little things
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2019-03-24 16:04:55 -04:00 |
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WilliamMiceli
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f17a0c8954
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Replaced missing simulation configuration file
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2019-03-24 15:52:26 -04:00 |
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jose.rodriguezlabra
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27f6d24b88
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/impl_1/gen_run.xml
# lab2CA.runs/synth_1/gen_run.xml
# lab2CA.sim/sim_1/behav/xsim/xelab.pb
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.sim/sim_1/behav/xsim/xvlog.pb
# lab2CA.srcs/sources_1/new/instructionMemory.v
# lab2CA.xpr
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2019-03-24 14:17:59 -04:00 |
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jose.rodriguezlabra
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94f0267a13
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stuff
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2019-03-24 14:16:03 -04:00 |
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Johannes
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ee9e420365
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Added string compare to instruction and data memory
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2019-03-24 14:14:28 -04:00 |
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Johannes
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395a8b6f8f
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Revert "metadata"
This reverts commit 191ca46f2d.
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2019-03-24 13:01:08 -04:00 |
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Johannes
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2af68f2731
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
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2019-03-24 12:59:29 -04:00 |
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Johannes
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a57af01a47
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Revert "Changed datamemory"
This reverts commit 90d9d69885.
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2019-03-24 12:49:08 -04:00 |
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Johannes
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90d9d69885
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Changed datamemory
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2019-03-24 12:47:18 -04:00 |
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jose.rodriguezlabra
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bab680ea27
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Added bank to CPU9bits
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2019-03-24 12:11:12 -04:00 |
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jose.rodriguezlabra
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191ca46f2d
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metadata
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2019-03-24 10:07:28 -04:00 |
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WilliamMiceli
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ad6765a43a
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BEQ Opcode fix & other stuffz
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2019-03-22 19:54:06 -04:00 |
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Johannes
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c85ad153dc
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Tested the instructions using the instruction memory
All of the instructions seem to be working other than beq. I might just be calling it wrong
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2019-03-20 12:08:24 -04:00 |
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Johannes
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0f55e62a2e
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
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2019-03-16 14:56:00 -04:00 |
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Johannes
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e8554a5a9a
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Minor changes to CPU
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2019-03-16 14:55:37 -04:00 |
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jose.rodriguezlabra
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eeb9c7c318
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Tested zero
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2019-03-16 14:55:11 -04:00 |
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Johannes
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fa5caec5dd
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Added memories to the CPU
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2019-03-16 14:37:46 -04:00 |
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jose.rodriguezlabra
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3c8147641f
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Added zeroing instr
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2019-03-16 14:34:36 -04:00 |
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Johannes
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21e846ab62
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Instruction & Data Memory
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2019-03-16 14:16:02 -04:00 |
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jose.rodriguezlabra
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dfd8753a62
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Implemented SEs
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2019-03-16 14:09:53 -04:00 |
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jose.rodriguezlabra
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5cbe490aae
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Added link instruction
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2019-03-16 14:01:32 -04:00 |
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WilliamMiceli
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934c73e899
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Small formatting change
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2019-03-16 13:44:44 -04:00 |
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WilliamMiceli
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b621f5a46b
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Added sign extension for 3 bits up to 8 bits
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2019-03-16 13:23:22 -04:00 |
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WilliamMiceli
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ef8b9c92e5
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Made testbench
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2019-03-16 13:02:29 -04:00 |
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WilliamMiceli
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c988ddb899
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Fixed 2 bit module
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2019-03-16 13:02:18 -04:00 |
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WilliamMiceli
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19ac8e130c
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Added sign extension for 2 bits into 9 bits, just to test first
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2019-03-16 12:55:57 -04:00 |
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jose.rodriguezlabra
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08e3659ba3
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Better Sim
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2019-03-14 14:37:58 -04:00 |
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jose.rodriguezlabra
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11a1d99e92
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Computer works (kinda)
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2019-03-13 12:51:44 -04:00 |
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jose.rodriguezlabra
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026eb65861
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Fixed bugs, finished BEQ, Added Halt
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2019-03-13 11:14:52 -04:00 |
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jose.rodriguezlabra
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911d8e31cc
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
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2019-03-13 09:01:33 -04:00 |
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jose.rodriguezlabra
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f6772daf04
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Worthless metadata
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2019-03-13 09:00:40 -04:00 |
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WilliamMiceli
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047efb7f1f
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More Vivado stuff
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2019-03-12 23:04:47 -04:00 |
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WilliamMiceli
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1e0e2bbf31
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Jose's awesome way to test zero structurally!
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2019-03-12 23:01:18 -04:00 |
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WilliamMiceli
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1efd958593
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Vivado stuff
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2019-03-12 22:56:03 -04:00 |
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WilliamMiceli
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dbdfc2cfc6
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Updated README
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2019-03-12 21:53:50 -04:00 |
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