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Author SHA1 Message Date
Johannes f34b3d4098 Update 2019-04-06 13:16:35 -04:00
Johannes 2746d6d49c Added pipeline registers 2019-04-06 13:13:47 -04:00
Johannes 65b951cf82 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	Bank_behav1.wcfg
#	lab2CA.runs/.jobs/vrs_config_42.xml
#	lab2CA.runs/impl_1/CPU9bits_tb.tcl
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/impl_1/htr.txt
#	lab2CA.runs/impl_1/init_design.pb
#	lab2CA.runs/impl_1/opt_design.pb
#	lab2CA.runs/impl_1/place_design.pb
#	lab2CA.runs/impl_1/vivado.jou
#	lab2CA.runs/impl_1/vivado.pb
#	lab2CA.runs/synth_1/CPU9bits.dcp
#	lab2CA.runs/synth_1/CPU9bits.vds
#	lab2CA.runs/synth_1/CPU9bits_tb.tcl
#	lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
#	lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.runs/synth_1/vivado.jou
#	lab2CA.runs/synth_1/vivado.pb
#	lab2CA.sim/sim_1/behav/xsim/webtalk.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 19:02:52 -04:00
Johannes be06f4e457 Just changes made for simulations 2019-03-24 18:55:49 -04:00
Johannes 033e606d5d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/dataMemory.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 17:08:42 -04:00
Johannes 03df69372a String Compare Working 2019-03-24 17:05:09 -04:00
Johannes 9a2e84bda6 metadata 2019-03-24 16:09:40 -04:00
Johannes ace0eca65a Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.xpr
 2019-03-24 16:06:29 -04:00
Johannes e8ada91e08 BEQ and LD fix 2019-03-24 16:05:16 -04:00
Johannes ee9e420365 Added string compare to instruction and data memory 2019-03-24 14:14:28 -04:00
Johannes 395a8b6f8f Revert "metadata" 
This reverts commit 191ca46f2d.
 2019-03-24 13:01:08 -04:00
Johannes 2af68f2731 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-03-24 12:59:29 -04:00
Johannes a57af01a47 Revert "Changed datamemory" 
This reverts commit 90d9d69885.
 2019-03-24 12:49:08 -04:00
Johannes 90d9d69885 Changed datamemory 2019-03-24 12:47:18 -04:00
Johannes c85ad153dc Tested the instructions using the instruction memory 
All of the instructions seem to be working other than beq. I might just be calling it wrong
 2019-03-20 12:08:24 -04:00
Johannes 0f55e62a2e Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-03-16 14:56:00 -04:00
Johannes e8554a5a9a Minor changes to CPU 2019-03-16 14:55:37 -04:00
Johannes fa5caec5dd Added memories to the CPU 2019-03-16 14:37:46 -04:00
Johannes 21e846ab62 Instruction & Data Memory 2019-03-16 14:16:02 -04:00
Johannes a9a4e81c6c Removed my behavioral slt 2019-03-12 21:33:24 -04:00
Johannes 735970454a My set less than was behavioral which is a no no 
# Conflicts:
#	lab2CA.srcs/sources_1/new/ALU.v
 2019-03-12 21:30:00 -04:00
Johannes cb91f6656a Many Changes 
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
 2019-03-12 21:14:27 -04:00
Johannes 3f01492398 Added SLT 
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
 2019-03-12 19:49:46 -04:00
Johannes 460fc3e4ed CPU 
LOTS
 2019-03-10 16:32:25 -04:00
goochey c047c801aa Lots of changes 
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
 2019-02-27 12:06:17 -05:00
goochey 82bcddf241 Merge remote-tracking branch 'origin/master' 2019-02-20 12:36:22 -05:00
goochey 9ba63880bd Fetch-Top 2019-02-20 11:40:43 -05:00
goochey 6550b48599 fetch unit test 2019-02-20 11:31:25 -05:00
goochey 54cccd419f Lots 
Lots
 2019-02-16 17:40:18 -05:00
goochey faf9f883dd Collaborative - Fixes and Testbenches for Basic Modules so far 2019-02-16 16:29:12 -05:00
goochey b2eb0da26c Fetch Unit Again 
I think I did it wrong
 2019-02-16 12:36:26 -05:00
goochey 34376a588e fetch unit 
Should be done. also added 2 to 1 mux
 2019-02-16 12:28:49 -05:00
goochey 1691adf1b5 fetch unit 
A little fetch unit
 2019-02-15 11:20:14 -05:00