460fc3e4ed
CPU
...
LOTS
2019-03-10 16:32:25 -04:00
7406cddb64
case for control unit
2019-03-10 14:05:21 -04:00
172238b4e0
Created CPU9bits file
2019-03-10 13:42:30 -04:00
8a903ebcfd
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# regFile_tb_behav.wcfg
2019-03-10 13:00:12 -04:00
4c19de70bc
Metadatapush
2019-03-10 12:59:09 -04:00
c047c801aa
Lots of changes
...
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
2019-02-27 12:06:17 -05:00
0104b0e689
Possible mistake
2019-02-25 13:30:58 -05:00
39b9ea781e
Removed MUX 16:1 as it's not needed
2019-02-25 13:28:28 -05:00
1734d58b47
Adjusted indentation of testbench code
2019-02-25 13:27:22 -05:00
7c83a77713
Activated all testbenches
2019-02-25 12:51:34 -05:00
cb30ee7e0a
Added list of fixes and things we need to do/implement
2019-02-21 15:11:35 -05:00
f9970dec06
Excluded Markdown files
2019-02-21 15:11:10 -05:00
6900e74405
Miscellaneous
2019-02-21 15:09:00 -05:00
82bcddf241
Merge remote-tracking branch 'origin/master'
2019-02-20 12:36:22 -05:00
9ba63880bd
Fetch-Top
2019-02-20 11:40:43 -05:00
6550b48599
fetch unit test
2019-02-20 11:31:25 -05:00
962374d58f
Looks like these aren't needed/were deleted from the project, just not the files.
2019-02-19 21:15:27 -05:00
54cccd419f
Lots
...
Lots
2019-02-16 17:40:18 -05:00
faf9f883dd
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
84e3725fdb
new thing
2019-02-16 13:04:06 -05:00
0d9cc2b890
Erased weird numbers
2019-02-16 12:50:02 -05:00
d60aa9d1e8
more stuff
2019-02-16 12:42:09 -05:00
22bf2728ba
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.srcs/sources_1/new/BasicModules.v
2019-02-16 12:39:15 -05:00
9aa7a5f0b0
stuff
2019-02-16 12:37:12 -05:00
b2eb0da26c
Fetch Unit Again
...
I think I did it wrong
2019-02-16 12:36:26 -05:00
bb578e7264
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/.jobs/vrs_config_1.xml
# lab2CA.runs/.jobs/vrs_config_2.xml
# lab2CA.srcs/sources_1/new/BasicModules.v
2019-02-16 12:33:12 -05:00
34376a588e
fetch unit
...
Should be done. also added 2 to 1 mux
2019-02-16 12:28:49 -05:00
5458d27391
Vivado data stuff
2019-02-15 17:51:58 -05:00
0b71b05c02
All current arithmetic and logical operations are now implemented
2019-02-15 17:51:05 -05:00
456fcf0804
Few renames; added left and right shifts, possibly some other stuff
2019-02-15 17:50:30 -05:00
6369170e41
Comments and slight renames
2019-02-15 17:49:12 -05:00
32faa621d6
Added Two's Compliment module
2019-02-15 17:18:54 -05:00
b2dfc05db8
Renamed some things; adder is now implemented in ALU
2019-02-15 17:09:44 -05:00
d6cee0483c
ALU opcode is different from instruction opcode, so reducing to needed operations only
2019-02-15 17:02:54 -05:00
582c80998e
Added 8:1 MUX
2019-02-15 17:02:11 -05:00
d1aa8e4ffb
Added outputs to the MUXes for the registers
2019-02-15 17:01:43 -05:00
f4c923f60c
Fixed ALU to use the inputs we're actually going to be giving it
2019-02-15 16:19:42 -05:00
393f7e7fc5
Added 1-bit and 9-bit OR and NOR modules
2019-02-15 16:16:13 -05:00
365fb5f648
Moved ALU from simulation sources to design sources
2019-02-15 16:15:41 -05:00
10e9e0b359
Added 1-bit NOR
2019-02-15 16:05:07 -05:00
68bb7a87e8
Framework of ALU is pretty much done
2019-02-15 15:57:04 -05:00
9628b971d7
Fixed a few syntax errors
2019-02-15 15:40:20 -05:00
fd22d5c7e6
Added 16:1 MUX for our ALU
2019-02-15 15:33:02 -05:00
cadbc4dd25
Added 9-bit NOT
2019-02-15 15:20:12 -05:00
8b37bee087
Added 9-bit AND module
2019-02-15 15:13:40 -05:00
2a84458894
Added 9-bit adder
2019-02-15 15:07:25 -05:00
81cdf3c62b
Added AND gate module
2019-02-15 14:59:38 -05:00
9eec4cdc76
Renamed mux in case we need different kinds later on
2019-02-15 14:56:34 -05:00
3d8ae740f0
Added 1-bit adder
2019-02-15 14:55:11 -05:00
8d78924c04
Added inverter
2019-02-15 14:50:42 -05:00
Johannes
jose.rodriguezlabra
WilliamMiceli
WilliamMiceli