William/WMU-ECE-3570-Lab
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08e3659ba39944b1f75799f904c92ce0764da640
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48 Commits

Author SHA1 Message Date
jose.rodriguezlabra
08e3659ba3 Better Sim 2019-03-14 14:37:58 -04:00
jose.rodriguezlabra
11a1d99e92 Computer works (kinda) 2019-03-13 12:51:44 -04:00
jose.rodriguezlabra
026eb65861 Fixed bugs, finished BEQ, Added Halt 2019-03-13 11:14:52 -04:00
WilliamMiceli
1e0e2bbf31 Jose's awesome way to test zero structurally! 2019-03-12 23:01:18 -04:00
Johannes
a9a4e81c6c Removed my behavioral slt 2019-03-12 21:33:24 -04:00
Johannes
735970454a My set less than was behavioral which is a no no 
# Conflicts:
#	lab2CA.srcs/sources_1/new/ALU.v
 2019-03-12 21:30:00 -04:00
WilliamMiceli
76bc5e006e Hopefully this is right. Vivado tells me it's fine, then minutes later not... 2019-03-12 21:21:52 -04:00
Johannes
cb91f6656a Many Changes 
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
 2019-03-12 21:14:27 -04:00
Johannes
3f01492398 Added SLT 
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
 2019-03-12 19:49:46 -04:00
WilliamMiceli
97433c3691 Shift right arithmetic implemented into ALU 2019-03-12 11:17:03 -04:00
WilliamMiceli
1c5e79c1ec Made 16:1 MUX for ALU's 4-bit opcode 2019-03-12 11:08:22 -04:00
WilliamMiceli
9e9ff7935b Renamed shifting for incoming shift_right_arithmetic 2019-03-12 10:54:45 -04:00
WilliamMiceli
f3ea596086 Simplified bitwise OR 2019-03-12 10:48:50 -04:00
WilliamMiceli
e01d639fa0 Simplified bitwise NOT 2019-03-12 10:47:25 -04:00
WilliamMiceli
a555728a48 Simplified bitwise NOR 2019-03-12 10:46:08 -04:00
WilliamMiceli
9519460187 AND is bitwise, so simplified, removing 1-bit modules 2019-03-12 10:43:16 -04:00
goochey
c047c801aa Lots of changes 
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
 2019-02-27 12:06:17 -05:00
WilliamMiceli
0104b0e689 Possible mistake 2019-02-25 13:30:58 -05:00
WilliamMiceli
39b9ea781e Removed MUX 16:1 as it's not needed 2019-02-25 13:28:28 -05:00
WilliamMiceli
1734d58b47 Adjusted indentation of testbench code 2019-02-25 13:27:22 -05:00
WilliamMiceli
7c83a77713 Activated all testbenches 2019-02-25 12:51:34 -05:00
goochey
6550b48599 fetch unit test 2019-02-20 11:31:25 -05:00
goochey
54cccd419f Lots 
Lots
 2019-02-16 17:40:18 -05:00
goochey
faf9f883dd Collaborative - Fixes and Testbenches for Basic Modules so far 2019-02-16 16:29:12 -05:00
jose.rodriguezlabra
84e3725fdb new thing 2019-02-16 13:04:06 -05:00
jose.rodriguezlabra
0d9cc2b890 Erased weird numbers 2019-02-16 12:50:02 -05:00
jose.rodriguezlabra
22bf2728ba Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.srcs/sources_1/new/BasicModules.v
 2019-02-16 12:39:15 -05:00
goochey
b2eb0da26c Fetch Unit Again 
I think I did it wrong
 2019-02-16 12:36:26 -05:00
jose.rodriguezlabra
bb578e7264 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/.jobs/vrs_config_1.xml
#	lab2CA.runs/.jobs/vrs_config_2.xml
#	lab2CA.srcs/sources_1/new/BasicModules.v
 2019-02-16 12:33:12 -05:00
WilliamMiceli
456fcf0804 Few renames; added left and right shifts, possibly some other stuff 2019-02-15 17:50:30 -05:00
WilliamMiceli
32faa621d6 Added Two's Compliment module 2019-02-15 17:18:54 -05:00
WilliamMiceli
582c80998e Added 8:1 MUX 2019-02-15 17:02:11 -05:00
WilliamMiceli
393f7e7fc5 Added 1-bit and 9-bit OR and NOR modules 2019-02-15 16:16:13 -05:00
WilliamMiceli
10e9e0b359 Added 1-bit NOR 2019-02-15 16:05:07 -05:00
WilliamMiceli
9628b971d7 Fixed a few syntax errors 2019-02-15 15:40:20 -05:00
WilliamMiceli
fd22d5c7e6 Added 16:1 MUX for our ALU 2019-02-15 15:33:02 -05:00
WilliamMiceli
cadbc4dd25 Added 9-bit NOT 2019-02-15 15:20:12 -05:00
WilliamMiceli
8b37bee087 Added 9-bit AND module 2019-02-15 15:13:40 -05:00
WilliamMiceli
2a84458894 Added 9-bit adder 2019-02-15 15:07:25 -05:00
WilliamMiceli
81cdf3c62b Added AND gate module 2019-02-15 14:59:38 -05:00
WilliamMiceli
9eec4cdc76 Renamed mux in case we need different kinds later on 2019-02-15 14:56:34 -05:00
WilliamMiceli
3d8ae740f0 Added 1-bit adder 2019-02-15 14:55:11 -05:00
WilliamMiceli
8d78924c04 Added inverter 2019-02-15 14:50:42 -05:00
WilliamMiceli
4421b1a9d6 Reordered into alphabetical order 2019-02-15 14:48:57 -05:00
WilliamMiceli
cdb52f35bd Converted MUX to use case statement 2019-02-15 14:46:08 -05:00
WilliamMiceli
337bf5cf13 Removed comment blocks 2019-02-15 14:34:59 -05:00
jose.rodriguezlabra
0b358a6c41 Set some comments 2019-02-15 12:38:07 -05:00
jose.rodriguezlabra
7aa2cfff2a Modularized project; mux, clock, and reg done; Progress on RegFile 2019-02-15 12:24:26 -05:00