William/WMU-ECE-3570-Lab
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Author SHA1 Message Date
WilliamMiceli
1efd958593 Vivado stuff 2019-03-12 22:56:03 -04:00
WilliamMiceli
dbdfc2cfc6 Updated README 2019-03-12 21:53:50 -04:00
Johannes
a9a4e81c6c Removed my behavioral slt 2019-03-12 21:33:24 -04:00
Johannes
735970454a My set less than was behavioral which is a no no 
# Conflicts:
#	lab2CA.srcs/sources_1/new/ALU.v
 2019-03-12 21:30:00 -04:00
WilliamMiceli
76bc5e006e Hopefully this is right. Vivado tells me it's fine, then minutes later not... 2019-03-12 21:21:52 -04:00
Johannes
cb91f6656a Many Changes 
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
 2019-03-12 21:14:27 -04:00
Johannes
3f01492398 Added SLT 
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
 2019-03-12 19:49:46 -04:00
WilliamMiceli
4a462752e9 Include NOT in the ALU 2019-03-12 11:23:48 -04:00
WilliamMiceli
97433c3691 Shift right arithmetic implemented into ALU 2019-03-12 11:17:03 -04:00
WilliamMiceli
fe1abc30c5 Fixed ALU testbench to 4-bit 2019-03-12 11:12:39 -04:00
WilliamMiceli
9ac8963fb0 ALU now fully has 4-bit opcode 2019-03-12 11:12:21 -04:00
WilliamMiceli
1c5e79c1ec Made 16:1 MUX for ALU's 4-bit opcode 2019-03-12 11:08:22 -04:00
WilliamMiceli
9d759edbec ALU now has 4 bits of it's own opcode 2019-03-12 11:07:50 -04:00
WilliamMiceli
9e9ff7935b Renamed shifting for incoming shift_right_arithmetic 2019-03-12 10:54:45 -04:00
WilliamMiceli
f3ea596086 Simplified bitwise OR 2019-03-12 10:48:50 -04:00
WilliamMiceli
e01d639fa0 Simplified bitwise NOT 2019-03-12 10:47:25 -04:00
WilliamMiceli
a555728a48 Simplified bitwise NOR 2019-03-12 10:46:08 -04:00
WilliamMiceli
9519460187 AND is bitwise, so simplified, removing 1-bit modules 2019-03-12 10:43:16 -04:00
Johannes
460fc3e4ed CPU 
LOTS
 2019-03-10 16:32:25 -04:00
jose.rodriguezlabra
7406cddb64 case for control unit 2019-03-10 14:05:21 -04:00
jose.rodriguezlabra
172238b4e0 Created CPU9bits file 2019-03-10 13:42:30 -04:00
jose.rodriguezlabra
8a903ebcfd Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	regFile_tb_behav.wcfg
 2019-03-10 13:00:12 -04:00
jose.rodriguezlabra
4c19de70bc Metadatapush 2019-03-10 12:59:09 -04:00
goochey
c047c801aa Lots of changes 
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
 2019-02-27 12:06:17 -05:00
WilliamMiceli
0104b0e689 Possible mistake 2019-02-25 13:30:58 -05:00
WilliamMiceli
39b9ea781e Removed MUX 16:1 as it's not needed 2019-02-25 13:28:28 -05:00
WilliamMiceli
1734d58b47 Adjusted indentation of testbench code 2019-02-25 13:27:22 -05:00
WilliamMiceli
7c83a77713 Activated all testbenches 2019-02-25 12:51:34 -05:00
WilliamMiceli
cb30ee7e0a Added list of fixes and things we need to do/implement 2019-02-21 15:11:35 -05:00
WilliamMiceli
f9970dec06 Excluded Markdown files 2019-02-21 15:11:10 -05:00
WilliamMiceli
6900e74405 Miscellaneous 2019-02-21 15:09:00 -05:00
goochey
82bcddf241 Merge remote-tracking branch 'origin/master' 2019-02-20 12:36:22 -05:00
goochey
9ba63880bd Fetch-Top 2019-02-20 11:40:43 -05:00
goochey
6550b48599 fetch unit test 2019-02-20 11:31:25 -05:00
WilliamMiceli
962374d58f Looks like these aren't needed/were deleted from the project, just not the files. 2019-02-19 21:15:27 -05:00
goochey
54cccd419f Lots 
Lots
 2019-02-16 17:40:18 -05:00
goochey
faf9f883dd Collaborative - Fixes and Testbenches for Basic Modules so far 2019-02-16 16:29:12 -05:00
jose.rodriguezlabra
84e3725fdb new thing 2019-02-16 13:04:06 -05:00
jose.rodriguezlabra
0d9cc2b890 Erased weird numbers 2019-02-16 12:50:02 -05:00
jose.rodriguezlabra
d60aa9d1e8 more stuff 2019-02-16 12:42:09 -05:00
jose.rodriguezlabra
22bf2728ba Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.srcs/sources_1/new/BasicModules.v
 2019-02-16 12:39:15 -05:00
jose.rodriguezlabra
9aa7a5f0b0 stuff 2019-02-16 12:37:12 -05:00
goochey
b2eb0da26c Fetch Unit Again 
I think I did it wrong
 2019-02-16 12:36:26 -05:00
jose.rodriguezlabra
bb578e7264 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/.jobs/vrs_config_1.xml
#	lab2CA.runs/.jobs/vrs_config_2.xml
#	lab2CA.srcs/sources_1/new/BasicModules.v
 2019-02-16 12:33:12 -05:00
goochey
34376a588e fetch unit 
Should be done. also added 2 to 1 mux
 2019-02-16 12:28:49 -05:00
WilliamMiceli
5458d27391 Vivado data stuff 2019-02-15 17:51:58 -05:00
WilliamMiceli
0b71b05c02 All current arithmetic and logical operations are now implemented 2019-02-15 17:51:05 -05:00
WilliamMiceli
456fcf0804 Few renames; added left and right shifts, possibly some other stuff 2019-02-15 17:50:30 -05:00
WilliamMiceli
6369170e41 Comments and slight renames 2019-02-15 17:49:12 -05:00
WilliamMiceli
32faa621d6 Added Two's Compliment module 2019-02-15 17:18:54 -05:00