Commit Graph

186 Commits

Author SHA1 Message Date
jose.rodriguezlabra bf57055518 metadat 2019-04-12 00:02:54 -04:00
jose.rodriguezlabra ddf47c7eee Tweaked forwarding check. Program 3 works with a few stalls 2019-04-12 00:01:27 -04:00
jose.rodriguezlabra 0118debfb9 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
#	CPU9bits_tb_behav.wcfg
#	lab2CA.xpr
2019-04-11 21:14:55 -04:00
jose.rodriguezlabra 0b4554a844 Fixed P3 mem and other 2019-04-11 21:13:57 -04:00
WilliamMiceli aa25f8fd0d Added stuff to waveform configuration 2019-04-11 19:57:38 -04:00
Johannes a3064a836b Nonsense 2019-04-11 19:23:15 -04:00
Johannes bc9c02322c Added forwarding 2019-04-11 18:36:00 -04:00
jose.rodriguezlabra 42d2bf2d80 Fixed pip enables, fixed Nop/Halt 2019-04-11 17:32:17 -04:00
WilliamMiceli b1f1a7339b Minor adjustments 2019-04-10 12:52:42 -04:00
WilliamMiceli a1887d7baf Mostly fixed waveform configuration 2019-04-10 12:52:21 -04:00
WilliamMiceli 847121e65a Not needed 2019-04-10 12:51:47 -04:00
WilliamMiceli f6e59802af Jumping is not working properly 2019-04-10 12:51:30 -04:00
WilliamMiceli eaec5f0883 Vivado stuff 2019-04-10 12:51:15 -04:00
Johannes 616dac4d29 Changes 2019-04-06 17:54:50 -04:00
Johannes e6cb8e536b Added Pipeline 2019-04-06 17:51:44 -04:00
WilliamMiceli e937485bd4 Vivado stuff 2019-04-06 17:44:26 -04:00
WilliamMiceli 93d5687a12 Stopped Vivado from whinning 2019-04-06 17:44:08 -04:00
WilliamMiceli 809bca06bf Vivado metadata 2019-04-06 16:09:17 -04:00
WilliamMiceli 858c1b8e98 Added a lot of points 2019-04-06 16:09:05 -04:00
WilliamMiceli dd7a319e92 Better indentation 2019-04-06 16:08:02 -04:00
WilliamMiceli 3fb02d18e3 Added result, found that waiting 50000 ns is not necessary, as there's a button for it 2019-04-06 16:07:32 -04:00
WilliamMiceli 4aad1aaaf7 Indented better 2019-04-06 16:06:49 -04:00
WilliamMiceli b3e2adb097 Updated simulation 2019-04-06 16:05:47 -04:00
WilliamMiceli c99ae69213 Vivado stuff 2019-04-06 16:05:24 -04:00
WilliamMiceli e79e0cf74d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-04-06 14:19:45 -04:00
WilliamMiceli 2c2132fb9f Vivado metadata 2019-04-06 14:19:20 -04:00
WilliamMiceli 7715bb2a9c Fixed simulation graphs 2019-04-06 14:19:10 -04:00
WilliamMiceli 31f0d8a9fc Enabled Bubble Sort for testing 2019-04-06 14:18:43 -04:00
WilliamMiceli 3129880d50 Enabled test data for Program 1 2019-04-06 14:18:18 -04:00
WilliamMiceli 7c3f8c6da9 Condensed a little bit. Maybe we can get the first instruction to work 2019-04-06 14:17:47 -04:00
WilliamMiceli f4b2ddebc1 Added back enable signals 2019-04-06 14:17:10 -04:00
WilliamMiceli de8740a231 Vivado runs/sim 2019-04-06 14:16:26 -04:00
WilliamMiceli b4f855c65b Reverting removing the enable signals to test if that is the issue 2019-04-06 14:15:51 -04:00
Johannes f34b3d4098 Update 2019-04-06 13:16:35 -04:00
Johannes 2746d6d49c Added pipeline registers 2019-04-06 13:13:47 -04:00
WilliamMiceli 443d01eba1 Modified sensitivities for result; Vivado metadata 2019-03-30 15:59:43 -04:00
WilliamMiceli ea0111542a Result output of CPU pretty much implemented; not yet tested 2019-03-29 18:16:45 -04:00
WilliamMiceli acf7f9e92b Registers and Banks don't need an enable, should be ignored using MUXes 2019-03-29 18:10:13 -04:00
WilliamMiceli 78f481f724 Vivado stuff 2019-03-29 17:29:24 -04:00
WilliamMiceli 71c6c2ad55 Fixed indentations 2019-03-29 17:28:50 -04:00
WilliamMiceli 2479eefa00 Formatted things to look a little nicer 2019-03-29 17:23:26 -04:00
WilliamMiceli 9fe8656d21 Increased memory size to get rid of unused address ports warning 2019-03-29 17:23:00 -04:00
WilliamMiceli 12700ed019 Simplified and removed latches 2019-03-29 17:22:32 -04:00
WilliamMiceli 9db4c1253b Fixed unconnected wires/ports 2019-03-29 17:22:06 -04:00
WilliamMiceli d8c7031e1b Fixed unconnected wires 2019-03-29 17:21:29 -04:00
WilliamMiceli db8ceeefb5 Now just need to get our programs working 2019-03-29 16:18:19 -04:00
WilliamMiceli 93469aa23f Reordered case statement by opcode and improved comment labels 2019-03-29 16:17:27 -04:00
WilliamMiceli 445f5ce830 Removed CLK, as it is not needed 2019-03-29 16:16:36 -04:00
WilliamMiceli 44c057e40d Simplified testbench a little 2019-03-29 16:16:11 -04:00
WilliamMiceli 20def71bb1 Removed references to CLK, as not needed; simplified testbench a little 2019-03-29 16:15:47 -04:00