 WilliamMiceli
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9fe8656d21
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Increased memory size to get rid of unused address ports warning
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2019-03-29 17:23:00 -04:00 |
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WilliamMiceli
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12700ed019
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Simplified and removed latches
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2019-03-29 17:22:32 -04:00 |
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WilliamMiceli
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9db4c1253b
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Fixed unconnected wires/ports
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2019-03-29 17:22:06 -04:00 |
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WilliamMiceli
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d8c7031e1b
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Fixed unconnected wires
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2019-03-29 17:21:29 -04:00 |
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WilliamMiceli
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db8ceeefb5
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Now just need to get our programs working
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2019-03-29 16:18:19 -04:00 |
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WilliamMiceli
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93469aa23f
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Reordered case statement by opcode and improved comment labels
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2019-03-29 16:17:27 -04:00 |
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WilliamMiceli
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445f5ce830
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Removed CLK, as it is not needed
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2019-03-29 16:16:36 -04:00 |
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WilliamMiceli
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44c057e40d
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Simplified testbench a little
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2019-03-29 16:16:11 -04:00 |
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WilliamMiceli
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20def71bb1
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Removed references to CLK, as not needed; simplified testbench a little
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2019-03-29 16:15:47 -04:00 |
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WilliamMiceli
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352aeefd1b
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Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM
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2019-03-29 16:13:50 -04:00 |
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WilliamMiceli
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5bd244f9ba
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Now Asynchronous and recognized by Vivado as RTL_ROM
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2019-03-29 16:13:07 -04:00 |
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WilliamMiceli
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5c165d603a
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Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven
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2019-03-29 16:11:52 -04:00 |
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WilliamMiceli
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03eb3f3740
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Commented out Program 1 test
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2019-03-29 14:57:29 -04:00 |
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WilliamMiceli
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ce86652a00
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Aded list of things to fix
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2019-03-25 18:04:44 -04:00 |
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WilliamMiceli
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97fcfb7ef1
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Fixed equation solver instructions
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2019-03-25 17:08:22 -04:00 |
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WilliamMiceli
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2420d52fc3
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Added test data for programs to run
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2019-03-25 16:00:32 -04:00 |
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WilliamMiceli
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5353c8c22e
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/CPU9bits.v
# lab2CA.srcs/sources_1/new/dataMemory.v
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2019-03-24 19:31:28 -04:00 |
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WilliamMiceli
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7490815502
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Making fixes to Bubble Sort
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2019-03-24 19:27:59 -04:00 |
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WilliamMiceli
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4354aebf8c
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Merged files
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2019-03-24 17:43:32 -04:00 |
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WilliamMiceli
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681c506eec
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Renamed signals on simulation waveforms
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2019-03-24 17:42:38 -04:00 |
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WilliamMiceli
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1c44d8d964
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Added comments to insructions
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2019-03-24 17:26:44 -04:00 |
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WilliamMiceli
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8e72409386
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Added Bubble Sort instructions and initial data memory
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2019-03-24 16:54:06 -04:00 |
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WilliamMiceli
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a978e1fbc6
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Revert file
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2019-03-24 16:11:31 -04:00 |
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WilliamMiceli
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f17a0c8954
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Replaced missing simulation configuration file
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2019-03-24 15:52:26 -04:00 |
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WilliamMiceli
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ad6765a43a
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BEQ Opcode fix & other stuffz
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2019-03-22 19:54:06 -04:00 |
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WilliamMiceli
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934c73e899
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Small formatting change
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2019-03-16 13:44:44 -04:00 |
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WilliamMiceli
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b621f5a46b
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Added sign extension for 3 bits up to 8 bits
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2019-03-16 13:23:22 -04:00 |
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WilliamMiceli
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ef8b9c92e5
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Made testbench
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2019-03-16 13:02:29 -04:00 |
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WilliamMiceli
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c988ddb899
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Fixed 2 bit module
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2019-03-16 13:02:18 -04:00 |
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WilliamMiceli
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19ac8e130c
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Added sign extension for 2 bits into 9 bits, just to test first
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2019-03-16 12:55:57 -04:00 |
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WilliamMiceli
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047efb7f1f
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More Vivado stuff
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2019-03-12 23:04:47 -04:00 |
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WilliamMiceli
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1e0e2bbf31
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Jose's awesome way to test zero structurally!
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2019-03-12 23:01:18 -04:00 |
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WilliamMiceli
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1efd958593
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Vivado stuff
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2019-03-12 22:56:03 -04:00 |
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WilliamMiceli
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dbdfc2cfc6
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Updated README
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2019-03-12 21:53:50 -04:00 |
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WilliamMiceli
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76bc5e006e
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Hopefully this is right. Vivado tells me it's fine, then minutes later not...
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2019-03-12 21:21:52 -04:00 |
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WilliamMiceli
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4a462752e9
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Include NOT in the ALU
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2019-03-12 11:23:48 -04:00 |
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WilliamMiceli
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97433c3691
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Shift right arithmetic implemented into ALU
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2019-03-12 11:17:03 -04:00 |
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WilliamMiceli
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fe1abc30c5
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Fixed ALU testbench to 4-bit
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2019-03-12 11:12:39 -04:00 |
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WilliamMiceli
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9ac8963fb0
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ALU now fully has 4-bit opcode
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2019-03-12 11:12:21 -04:00 |
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WilliamMiceli
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1c5e79c1ec
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Made 16:1 MUX for ALU's 4-bit opcode
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2019-03-12 11:08:22 -04:00 |
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WilliamMiceli
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9d759edbec
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ALU now has 4 bits of it's own opcode
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2019-03-12 11:07:50 -04:00 |
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WilliamMiceli
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9e9ff7935b
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Renamed shifting for incoming shift_right_arithmetic
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2019-03-12 10:54:45 -04:00 |
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WilliamMiceli
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f3ea596086
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Simplified bitwise OR
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2019-03-12 10:48:50 -04:00 |
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WilliamMiceli
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e01d639fa0
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Simplified bitwise NOT
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2019-03-12 10:47:25 -04:00 |
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WilliamMiceli
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a555728a48
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Simplified bitwise NOR
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2019-03-12 10:46:08 -04:00 |
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WilliamMiceli
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9519460187
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AND is bitwise, so simplified, removing 1-bit modules
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2019-03-12 10:43:16 -04:00 |
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WilliamMiceli
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0104b0e689
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Possible mistake
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2019-02-25 13:30:58 -05:00 |
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WilliamMiceli
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39b9ea781e
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Removed MUX 16:1 as it's not needed
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2019-02-25 13:28:28 -05:00 |
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WilliamMiceli
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1734d58b47
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Adjusted indentation of testbench code
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2019-02-25 13:27:22 -05:00 |
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WilliamMiceli
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7c83a77713
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Activated all testbenches
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2019-02-25 12:51:34 -05:00 |
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WilliamMiceli
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cb30ee7e0a
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Added list of fixes and things we need to do/implement
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2019-02-21 15:11:35 -05:00 |
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WilliamMiceli
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f9970dec06
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Excluded Markdown files
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2019-02-21 15:11:10 -05:00 |
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WilliamMiceli
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6900e74405
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Miscellaneous
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2019-02-21 15:09:00 -05:00 |
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