jose.rodriguezlabra
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0b4554a844
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Fixed P3 mem and other
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2019-04-11 21:13:57 -04:00 |
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Johannes
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a3064a836b
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Nonsense
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2019-04-11 19:23:15 -04:00 |
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Johannes
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bc9c02322c
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Added forwarding
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2019-04-11 18:36:00 -04:00 |
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jose.rodriguezlabra
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42d2bf2d80
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Fixed pip enables, fixed Nop/Halt
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2019-04-11 17:32:17 -04:00 |
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WilliamMiceli
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b1f1a7339b
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Minor adjustments
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2019-04-10 12:52:42 -04:00 |
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WilliamMiceli
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a1887d7baf
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Mostly fixed waveform configuration
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2019-04-10 12:52:21 -04:00 |
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WilliamMiceli
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847121e65a
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Not needed
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2019-04-10 12:51:47 -04:00 |
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WilliamMiceli
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f6e59802af
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Jumping is not working properly
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2019-04-10 12:51:30 -04:00 |
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WilliamMiceli
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eaec5f0883
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Vivado stuff
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2019-04-10 12:51:15 -04:00 |
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Johannes
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616dac4d29
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Changes
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2019-04-06 17:54:50 -04:00 |
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Johannes
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e6cb8e536b
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Added Pipeline
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2019-04-06 17:51:44 -04:00 |
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WilliamMiceli
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e937485bd4
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Vivado stuff
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2019-04-06 17:44:26 -04:00 |
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WilliamMiceli
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93d5687a12
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Stopped Vivado from whinning
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2019-04-06 17:44:08 -04:00 |
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WilliamMiceli
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809bca06bf
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Vivado metadata
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2019-04-06 16:09:17 -04:00 |
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WilliamMiceli
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858c1b8e98
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Added a lot of points
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2019-04-06 16:09:05 -04:00 |
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WilliamMiceli
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dd7a319e92
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Better indentation
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2019-04-06 16:08:02 -04:00 |
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WilliamMiceli
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3fb02d18e3
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Added result, found that waiting 50000 ns is not necessary, as there's a button for it
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2019-04-06 16:07:32 -04:00 |
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WilliamMiceli
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4aad1aaaf7
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Indented better
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2019-04-06 16:06:49 -04:00 |
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WilliamMiceli
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b3e2adb097
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Updated simulation
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2019-04-06 16:05:47 -04:00 |
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WilliamMiceli
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c99ae69213
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Vivado stuff
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2019-04-06 16:05:24 -04:00 |
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WilliamMiceli
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e79e0cf74d
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
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2019-04-06 14:19:45 -04:00 |
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WilliamMiceli
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2c2132fb9f
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Vivado metadata
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2019-04-06 14:19:20 -04:00 |
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WilliamMiceli
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7715bb2a9c
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Fixed simulation graphs
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2019-04-06 14:19:10 -04:00 |
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WilliamMiceli
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31f0d8a9fc
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Enabled Bubble Sort for testing
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2019-04-06 14:18:43 -04:00 |
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WilliamMiceli
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3129880d50
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Enabled test data for Program 1
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2019-04-06 14:18:18 -04:00 |
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WilliamMiceli
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7c3f8c6da9
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Condensed a little bit. Maybe we can get the first instruction to work
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2019-04-06 14:17:47 -04:00 |
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WilliamMiceli
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f4b2ddebc1
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Added back enable signals
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2019-04-06 14:17:10 -04:00 |
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WilliamMiceli
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de8740a231
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Vivado runs/sim
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2019-04-06 14:16:26 -04:00 |
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WilliamMiceli
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b4f855c65b
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Reverting removing the enable signals to test if that is the issue
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2019-04-06 14:15:51 -04:00 |
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Johannes
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f34b3d4098
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Update
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2019-04-06 13:16:35 -04:00 |
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Johannes
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2746d6d49c
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Added pipeline registers
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2019-04-06 13:13:47 -04:00 |
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WilliamMiceli
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443d01eba1
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Modified sensitivities for result; Vivado metadata
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2019-03-30 15:59:43 -04:00 |
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WilliamMiceli
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ea0111542a
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Result output of CPU pretty much implemented; not yet tested
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2019-03-29 18:16:45 -04:00 |
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WilliamMiceli
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acf7f9e92b
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Registers and Banks don't need an enable, should be ignored using MUXes
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2019-03-29 18:10:13 -04:00 |
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WilliamMiceli
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78f481f724
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Vivado stuff
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2019-03-29 17:29:24 -04:00 |
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WilliamMiceli
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71c6c2ad55
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Fixed indentations
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2019-03-29 17:28:50 -04:00 |
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WilliamMiceli
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2479eefa00
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Formatted things to look a little nicer
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2019-03-29 17:23:26 -04:00 |
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WilliamMiceli
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9fe8656d21
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Increased memory size to get rid of unused address ports warning
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2019-03-29 17:23:00 -04:00 |
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WilliamMiceli
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12700ed019
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Simplified and removed latches
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2019-03-29 17:22:32 -04:00 |
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WilliamMiceli
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9db4c1253b
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Fixed unconnected wires/ports
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2019-03-29 17:22:06 -04:00 |
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WilliamMiceli
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d8c7031e1b
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Fixed unconnected wires
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2019-03-29 17:21:29 -04:00 |
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WilliamMiceli
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db8ceeefb5
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Now just need to get our programs working
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2019-03-29 16:18:19 -04:00 |
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WilliamMiceli
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93469aa23f
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Reordered case statement by opcode and improved comment labels
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2019-03-29 16:17:27 -04:00 |
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WilliamMiceli
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445f5ce830
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Removed CLK, as it is not needed
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2019-03-29 16:16:36 -04:00 |
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WilliamMiceli
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44c057e40d
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Simplified testbench a little
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2019-03-29 16:16:11 -04:00 |
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WilliamMiceli
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20def71bb1
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Removed references to CLK, as not needed; simplified testbench a little
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2019-03-29 16:15:47 -04:00 |
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WilliamMiceli
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352aeefd1b
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Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM
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2019-03-29 16:13:50 -04:00 |
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WilliamMiceli
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5bd244f9ba
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Now Asynchronous and recognized by Vivado as RTL_ROM
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2019-03-29 16:13:07 -04:00 |
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WilliamMiceli
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5c165d603a
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Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven
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2019-03-29 16:11:52 -04:00 |
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WilliamMiceli
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03eb3f3740
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Commented out Program 1 test
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2019-03-29 14:57:29 -04:00 |
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