William/WMU-ECE-3570-Lab
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  • dfd8753a62 Implemented SEs jose.rodriguezlabra 2019-03-16 14:09:53 -04:00
  • 5cbe490aae Added link instruction jose.rodriguezlabra 2019-03-16 14:01:32 -04:00
  • 934c73e899 Small formatting change WilliamMiceli 2019-03-16 13:44:44 -04:00
  • b621f5a46b Added sign extension for 3 bits up to 8 bits WilliamMiceli 2019-03-16 13:23:22 -04:00
  • ef8b9c92e5 Made testbench WilliamMiceli 2019-03-16 13:02:29 -04:00
  • c988ddb899 Fixed 2 bit module WilliamMiceli 2019-03-16 13:02:18 -04:00
  • 19ac8e130c Added sign extension for 2 bits into 9 bits, just to test first WilliamMiceli 2019-03-16 12:55:57 -04:00
  • 08e3659ba3 Better Sim jose.rodriguezlabra 2019-03-14 14:37:58 -04:00
  • 11a1d99e92 Computer works (kinda) jose.rodriguezlabra 2019-03-13 12:51:44 -04:00
  • 026eb65861 Fixed bugs, finished BEQ, Added Halt jose.rodriguezlabra 2019-03-13 11:14:52 -04:00
  • 911d8e31cc Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 jose.rodriguezlabra 2019-03-13 09:01:33 -04:00
  • f6772daf04 Worthless metadata jose.rodriguezlabra 2019-03-13 09:00:40 -04:00
  • 047efb7f1f More Vivado stuff WilliamMiceli 2019-03-12 23:04:47 -04:00
  • 1e0e2bbf31 Jose's awesome way to test zero structurally! WilliamMiceli 2019-03-12 23:01:18 -04:00
  • 1efd958593 Vivado stuff WilliamMiceli 2019-03-12 22:56:03 -04:00
  • dbdfc2cfc6 Updated README WilliamMiceli 2019-03-12 21:53:50 -04:00
  • a9a4e81c6c Removed my behavioral slt Johannes 2019-03-12 21:33:24 -04:00
  • 735970454a My set less than was behavioral which is a no no Johannes 2019-03-12 21:30:00 -04:00
  • 76bc5e006e Hopefully this is right. Vivado tells me it's fine, then minutes later not... WilliamMiceli 2019-03-12 21:21:52 -04:00
  • cb91f6656a Many Changes Johannes 2019-03-12 21:14:27 -04:00
  • 3f01492398 Added SLT Johannes 2019-03-12 19:49:46 -04:00
  • 4a462752e9 Include NOT in the ALU WilliamMiceli 2019-03-12 11:23:48 -04:00
  • 97433c3691 Shift right arithmetic implemented into ALU WilliamMiceli 2019-03-12 11:17:03 -04:00
  • fe1abc30c5 Fixed ALU testbench to 4-bit WilliamMiceli 2019-03-12 11:12:39 -04:00
  • 9ac8963fb0 ALU now fully has 4-bit opcode WilliamMiceli 2019-03-12 11:12:21 -04:00
  • 1c5e79c1ec Made 16:1 MUX for ALU's 4-bit opcode WilliamMiceli 2019-03-12 11:08:22 -04:00
  • 9d759edbec ALU now has 4 bits of it's own opcode WilliamMiceli 2019-03-12 11:07:50 -04:00
  • 9e9ff7935b Renamed shifting for incoming shift_right_arithmetic WilliamMiceli 2019-03-12 10:54:45 -04:00
  • f3ea596086 Simplified bitwise OR WilliamMiceli 2019-03-12 10:48:50 -04:00
  • e01d639fa0 Simplified bitwise NOT WilliamMiceli 2019-03-12 10:47:25 -04:00
  • a555728a48 Simplified bitwise NOR WilliamMiceli 2019-03-12 10:46:08 -04:00
  • 9519460187 AND is bitwise, so simplified, removing 1-bit modules WilliamMiceli 2019-03-12 10:43:16 -04:00
  • 460fc3e4ed CPU Johannes 2019-03-10 16:32:25 -04:00
  • 7406cddb64 case for control unit jose.rodriguezlabra 2019-03-10 14:05:21 -04:00
  • 172238b4e0 Created CPU9bits file jose.rodriguezlabra 2019-03-10 13:42:30 -04:00
  • 8a903ebcfd Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 jose.rodriguezlabra 2019-03-10 13:00:12 -04:00
  • 4c19de70bc Metadatapush jose.rodriguezlabra 2019-03-10 12:59:09 -04:00
  • c047c801aa Lots of changes goochey 2019-02-27 12:06:17 -05:00
  • 0104b0e689 Possible mistake WilliamMiceli 2019-02-25 13:30:58 -05:00
  • 39b9ea781e Removed MUX 16:1 as it's not needed WilliamMiceli 2019-02-25 13:28:28 -05:00
  • 1734d58b47 Adjusted indentation of testbench code WilliamMiceli 2019-02-25 13:27:22 -05:00
  • 7c83a77713 Activated all testbenches WilliamMiceli 2019-02-25 12:51:34 -05:00
  • cb30ee7e0a Added list of fixes and things we need to do/implement WilliamMiceli 2019-02-21 15:11:35 -05:00
  • f9970dec06 Excluded Markdown files WilliamMiceli 2019-02-21 15:11:10 -05:00
  • 6900e74405 Miscellaneous WilliamMiceli 2019-02-21 15:09:00 -05:00
  • 82bcddf241 Merge remote-tracking branch 'origin/master' goochey 2019-02-20 12:36:22 -05:00
  • 9ba63880bd Fetch-Top goochey 2019-02-20 11:40:43 -05:00
  • 6550b48599 fetch unit test goochey 2019-02-20 11:31:25 -05:00
  • 962374d58f Looks like these aren't needed/were deleted from the project, just not the files. WilliamMiceli 2019-02-19 21:15:27 -05:00
  • 54cccd419f Lots goochey 2019-02-16 17:40:18 -05:00
  • faf9f883dd Collaborative - Fixes and Testbenches for Basic Modules so far goochey 2019-02-16 16:29:12 -05:00
  • 84e3725fdb new thing jose.rodriguezlabra 2019-02-16 13:04:06 -05:00
  • 0d9cc2b890 Erased weird numbers jose.rodriguezlabra 2019-02-16 12:50:02 -05:00
  • d60aa9d1e8 more stuff jose.rodriguezlabra 2019-02-16 12:42:09 -05:00
  • 22bf2728ba Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 jose.rodriguezlabra 2019-02-16 12:39:15 -05:00
  • 9aa7a5f0b0 stuff jose.rodriguezlabra 2019-02-16 12:37:12 -05:00
  • b2eb0da26c Fetch Unit Again goochey 2019-02-16 12:36:26 -05:00
  • bb578e7264 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 jose.rodriguezlabra 2019-02-16 12:33:12 -05:00
  • 34376a588e fetch unit goochey 2019-02-16 12:28:49 -05:00
  • 5458d27391 Vivado data stuff WilliamMiceli 2019-02-15 17:51:58 -05:00
  • 0b71b05c02 All current arithmetic and logical operations are now implemented WilliamMiceli 2019-02-15 17:51:05 -05:00
  • 456fcf0804 Few renames; added left and right shifts, possibly some other stuff WilliamMiceli 2019-02-15 17:50:30 -05:00
  • 6369170e41 Comments and slight renames WilliamMiceli 2019-02-15 17:49:12 -05:00
  • 32faa621d6 Added Two's Compliment module WilliamMiceli 2019-02-15 17:18:54 -05:00
  • b2dfc05db8 Renamed some things; adder is now implemented in ALU WilliamMiceli 2019-02-15 17:09:44 -05:00
  • d6cee0483c ALU opcode is different from instruction opcode, so reducing to needed operations only WilliamMiceli 2019-02-15 17:02:54 -05:00
  • 582c80998e Added 8:1 MUX WilliamMiceli 2019-02-15 17:02:11 -05:00
  • d1aa8e4ffb Added outputs to the MUXes for the registers WilliamMiceli 2019-02-15 17:01:43 -05:00
  • f4c923f60c Fixed ALU to use the inputs we're actually going to be giving it WilliamMiceli 2019-02-15 16:19:42 -05:00
  • 393f7e7fc5 Added 1-bit and 9-bit OR and NOR modules WilliamMiceli 2019-02-15 16:16:13 -05:00
  • 365fb5f648 Moved ALU from simulation sources to design sources WilliamMiceli 2019-02-15 16:15:41 -05:00
  • 10e9e0b359 Added 1-bit NOR WilliamMiceli 2019-02-15 16:05:07 -05:00
  • 68bb7a87e8 Framework of ALU is pretty much done WilliamMiceli 2019-02-15 15:57:04 -05:00
  • 9628b971d7 Fixed a few syntax errors WilliamMiceli 2019-02-15 15:40:20 -05:00
  • fd22d5c7e6 Added 16:1 MUX for our ALU WilliamMiceli 2019-02-15 15:33:02 -05:00
  • cadbc4dd25 Added 9-bit NOT WilliamMiceli 2019-02-15 15:20:12 -05:00
  • 8b37bee087 Added 9-bit AND module WilliamMiceli 2019-02-15 15:13:40 -05:00
  • 2a84458894 Added 9-bit adder WilliamMiceli 2019-02-15 15:07:25 -05:00
  • 81cdf3c62b Added AND gate module WilliamMiceli 2019-02-15 14:59:38 -05:00
  • 9eec4cdc76 Renamed mux in case we need different kinds later on WilliamMiceli 2019-02-15 14:56:34 -05:00
  • 3d8ae740f0 Added 1-bit adder WilliamMiceli 2019-02-15 14:55:11 -05:00
  • 8d78924c04 Added inverter WilliamMiceli 2019-02-15 14:50:42 -05:00
  • 4421b1a9d6 Reordered into alphabetical order WilliamMiceli 2019-02-15 14:48:57 -05:00
  • cdb52f35bd Converted MUX to use case statement WilliamMiceli 2019-02-15 14:46:08 -05:00
  • 337bf5cf13 Removed comment blocks WilliamMiceli 2019-02-15 14:34:59 -05:00
  • 0b358a6c41 Set some comments jose.rodriguezlabra 2019-02-15 12:38:07 -05:00
  • 7aa2cfff2a Modularized project; mux, clock, and reg done; Progress on RegFile jose.rodriguezlabra 2019-02-15 12:24:26 -05:00
  • d147e12073 Forgot to stage this file jose.rodriguezlabra 2019-02-15 11:53:54 -05:00
  • 3378e5bfd8 Merge resolve? jose.rodriguezlabra 2019-02-15 11:53:29 -05:00
  • 1691adf1b5 fetch unit goochey 2019-02-15 11:20:14 -05:00
  • b93a3779cc First upload jose.rodriguezlabra 2019-02-08 18:18:54 -05:00
  • 0b9b2e00a5 Initial commit, gitignore William Miceli 2019-02-08 18:10:13 -05:00