William/WMU-ECE-3570-Lab
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Author SHA1 Message Date
Johannes
e6cb8e536b Added Pipeline 2019-04-06 17:51:44 -04:00
Johannes
f34b3d4098 Update 2019-04-06 13:16:35 -04:00
Johannes
2746d6d49c Added pipeline registers 2019-04-06 13:13:47 -04:00
WilliamMiceli
443d01eba1 Modified sensitivities for result; Vivado metadata 2019-03-30 15:59:43 -04:00
WilliamMiceli
ea0111542a Result output of CPU pretty much implemented; not yet tested 2019-03-29 18:16:45 -04:00
WilliamMiceli
acf7f9e92b Registers and Banks don't need an enable, should be ignored using MUXes 2019-03-29 18:10:13 -04:00
WilliamMiceli
78f481f724 Vivado stuff 2019-03-29 17:29:24 -04:00
WilliamMiceli
71c6c2ad55 Fixed indentations 2019-03-29 17:28:50 -04:00
WilliamMiceli
2479eefa00 Formatted things to look a little nicer 2019-03-29 17:23:26 -04:00
WilliamMiceli
9fe8656d21 Increased memory size to get rid of unused address ports warning 2019-03-29 17:23:00 -04:00
WilliamMiceli
12700ed019 Simplified and removed latches 2019-03-29 17:22:32 -04:00
WilliamMiceli
9db4c1253b Fixed unconnected wires/ports 2019-03-29 17:22:06 -04:00
WilliamMiceli
d8c7031e1b Fixed unconnected wires 2019-03-29 17:21:29 -04:00
WilliamMiceli
db8ceeefb5 Now just need to get our programs working 2019-03-29 16:18:19 -04:00
WilliamMiceli
93469aa23f Reordered case statement by opcode and improved comment labels 2019-03-29 16:17:27 -04:00
WilliamMiceli
445f5ce830 Removed CLK, as it is not needed 2019-03-29 16:16:36 -04:00
WilliamMiceli
44c057e40d Simplified testbench a little 2019-03-29 16:16:11 -04:00
WilliamMiceli
20def71bb1 Removed references to CLK, as not needed; simplified testbench a little 2019-03-29 16:15:47 -04:00
WilliamMiceli
352aeefd1b Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM 2019-03-29 16:13:50 -04:00
WilliamMiceli
5bd244f9ba Now Asynchronous and recognized by Vivado as RTL_ROM 2019-03-29 16:13:07 -04:00
WilliamMiceli
5c165d603a Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven 2019-03-29 16:11:52 -04:00
WilliamMiceli
03eb3f3740 Commented out Program 1 test 2019-03-29 14:57:29 -04:00
WilliamMiceli
ce86652a00 Aded list of things to fix 2019-03-25 18:04:44 -04:00
WilliamMiceli
97fcfb7ef1 Fixed equation solver instructions 2019-03-25 17:08:22 -04:00
WilliamMiceli
2420d52fc3 Added test data for programs to run 2019-03-25 16:00:32 -04:00
WilliamMiceli
5353c8c22e Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/CPU9bits.v
#	lab2CA.srcs/sources_1/new/dataMemory.v
 2019-03-24 19:31:28 -04:00
WilliamMiceli
7490815502 Making fixes to Bubble Sort 2019-03-24 19:27:59 -04:00
Johannes
65b951cf82 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	Bank_behav1.wcfg
#	lab2CA.runs/.jobs/vrs_config_42.xml
#	lab2CA.runs/impl_1/CPU9bits_tb.tcl
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/impl_1/htr.txt
#	lab2CA.runs/impl_1/init_design.pb
#	lab2CA.runs/impl_1/opt_design.pb
#	lab2CA.runs/impl_1/place_design.pb
#	lab2CA.runs/impl_1/vivado.jou
#	lab2CA.runs/impl_1/vivado.pb
#	lab2CA.runs/synth_1/CPU9bits.dcp
#	lab2CA.runs/synth_1/CPU9bits.vds
#	lab2CA.runs/synth_1/CPU9bits_tb.tcl
#	lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
#	lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.runs/synth_1/vivado.jou
#	lab2CA.runs/synth_1/vivado.pb
#	lab2CA.sim/sim_1/behav/xsim/webtalk.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 19:02:52 -04:00
Johannes
be06f4e457 Just changes made for simulations 2019-03-24 18:55:49 -04:00
WilliamMiceli
4354aebf8c Merged files 2019-03-24 17:43:32 -04:00
WilliamMiceli
681c506eec Renamed signals on simulation waveforms 2019-03-24 17:42:38 -04:00
jose.rodriguezlabra
5a506ba3ab Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 17:33:42 -04:00
jose.rodriguezlabra
efbd7b773b Binary Search completed 
It is not fully tested, but it looks pretty good
 2019-03-24 17:30:27 -04:00
WilliamMiceli
1c44d8d964 Added comments to insructions 2019-03-24 17:26:44 -04:00
Johannes
033e606d5d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/dataMemory.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 17:08:42 -04:00
Johannes
03df69372a String Compare Working 2019-03-24 17:05:09 -04:00
WilliamMiceli
8e72409386 Added Bubble Sort instructions and initial data memory 2019-03-24 16:54:06 -04:00
jose.rodriguezlabra
335280ccd5 Added Binary Search Code 2019-03-24 16:35:59 -04:00
WilliamMiceli
a978e1fbc6 Revert file 2019-03-24 16:11:31 -04:00
Johannes
9a2e84bda6 metadata 2019-03-24 16:09:40 -04:00
Johannes
ace0eca65a Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.xpr
 2019-03-24 16:06:29 -04:00
jose.rodriguezlabra
eac5d71dd6 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
 2019-03-24 16:05:40 -04:00
Johannes
e8ada91e08 BEQ and LD fix 2019-03-24 16:05:16 -04:00
jose.rodriguezlabra
ce2410e26c little things 2019-03-24 16:04:55 -04:00
WilliamMiceli
f17a0c8954 Replaced missing simulation configuration file 2019-03-24 15:52:26 -04:00
jose.rodriguezlabra
27f6d24b88 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 14:17:59 -04:00
jose.rodriguezlabra
94f0267a13 stuff 2019-03-24 14:16:03 -04:00
Johannes
ee9e420365 Added string compare to instruction and data memory 2019-03-24 14:14:28 -04:00
Johannes
395a8b6f8f Revert "metadata" 
This reverts commit 191ca46f2d.
 2019-03-24 13:01:08 -04:00
Johannes
2af68f2731 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-03-24 12:59:29 -04:00