William/WMU-ECE-3570-Lab
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847121e65aa9d383db0c644ed556eb897a7f800d
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Author SHA1 Message Date
WilliamMiceli
847121e65a Not needed 2019-04-10 12:51:47 -04:00
WilliamMiceli
f6e59802af Jumping is not working properly 2019-04-10 12:51:30 -04:00
WilliamMiceli
eaec5f0883 Vivado stuff 2019-04-10 12:51:15 -04:00
Johannes
616dac4d29 Changes 2019-04-06 17:54:50 -04:00
Johannes
e6cb8e536b Added Pipeline 2019-04-06 17:51:44 -04:00
WilliamMiceli
e937485bd4 Vivado stuff 2019-04-06 17:44:26 -04:00
WilliamMiceli
93d5687a12 Stopped Vivado from whinning 2019-04-06 17:44:08 -04:00
WilliamMiceli
809bca06bf Vivado metadata 2019-04-06 16:09:17 -04:00
WilliamMiceli
858c1b8e98 Added a lot of points 2019-04-06 16:09:05 -04:00
WilliamMiceli
dd7a319e92 Better indentation 2019-04-06 16:08:02 -04:00
WilliamMiceli
3fb02d18e3 Added result, found that waiting 50000 ns is not necessary, as there's a button for it 2019-04-06 16:07:32 -04:00
WilliamMiceli
4aad1aaaf7 Indented better 2019-04-06 16:06:49 -04:00
WilliamMiceli
b3e2adb097 Updated simulation 2019-04-06 16:05:47 -04:00
WilliamMiceli
c99ae69213 Vivado stuff 2019-04-06 16:05:24 -04:00
WilliamMiceli
e79e0cf74d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-04-06 14:19:45 -04:00
WilliamMiceli
2c2132fb9f Vivado metadata 2019-04-06 14:19:20 -04:00
WilliamMiceli
7715bb2a9c Fixed simulation graphs 2019-04-06 14:19:10 -04:00
WilliamMiceli
31f0d8a9fc Enabled Bubble Sort for testing 2019-04-06 14:18:43 -04:00
WilliamMiceli
3129880d50 Enabled test data for Program 1 2019-04-06 14:18:18 -04:00
WilliamMiceli
7c3f8c6da9 Condensed a little bit. Maybe we can get the first instruction to work 2019-04-06 14:17:47 -04:00
WilliamMiceli
f4b2ddebc1 Added back enable signals 2019-04-06 14:17:10 -04:00
WilliamMiceli
de8740a231 Vivado runs/sim 2019-04-06 14:16:26 -04:00
WilliamMiceli
b4f855c65b Reverting removing the enable signals to test if that is the issue 2019-04-06 14:15:51 -04:00
Johannes
f34b3d4098 Update 2019-04-06 13:16:35 -04:00
Johannes
2746d6d49c Added pipeline registers 2019-04-06 13:13:47 -04:00
WilliamMiceli
443d01eba1 Modified sensitivities for result; Vivado metadata 2019-03-30 15:59:43 -04:00
WilliamMiceli
ea0111542a Result output of CPU pretty much implemented; not yet tested 2019-03-29 18:16:45 -04:00
WilliamMiceli
acf7f9e92b Registers and Banks don't need an enable, should be ignored using MUXes 2019-03-29 18:10:13 -04:00
WilliamMiceli
78f481f724 Vivado stuff 2019-03-29 17:29:24 -04:00
WilliamMiceli
71c6c2ad55 Fixed indentations 2019-03-29 17:28:50 -04:00
WilliamMiceli
2479eefa00 Formatted things to look a little nicer 2019-03-29 17:23:26 -04:00
WilliamMiceli
9fe8656d21 Increased memory size to get rid of unused address ports warning 2019-03-29 17:23:00 -04:00
WilliamMiceli
12700ed019 Simplified and removed latches 2019-03-29 17:22:32 -04:00
WilliamMiceli
9db4c1253b Fixed unconnected wires/ports 2019-03-29 17:22:06 -04:00
WilliamMiceli
d8c7031e1b Fixed unconnected wires 2019-03-29 17:21:29 -04:00
WilliamMiceli
db8ceeefb5 Now just need to get our programs working 2019-03-29 16:18:19 -04:00
WilliamMiceli
93469aa23f Reordered case statement by opcode and improved comment labels 2019-03-29 16:17:27 -04:00
WilliamMiceli
445f5ce830 Removed CLK, as it is not needed 2019-03-29 16:16:36 -04:00
WilliamMiceli
44c057e40d Simplified testbench a little 2019-03-29 16:16:11 -04:00
WilliamMiceli
20def71bb1 Removed references to CLK, as not needed; simplified testbench a little 2019-03-29 16:15:47 -04:00
WilliamMiceli
352aeefd1b Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM 2019-03-29 16:13:50 -04:00
WilliamMiceli
5bd244f9ba Now Asynchronous and recognized by Vivado as RTL_ROM 2019-03-29 16:13:07 -04:00
WilliamMiceli
5c165d603a Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven 2019-03-29 16:11:52 -04:00
WilliamMiceli
03eb3f3740 Commented out Program 1 test 2019-03-29 14:57:29 -04:00
WilliamMiceli
ce86652a00 Aded list of things to fix 2019-03-25 18:04:44 -04:00
WilliamMiceli
97fcfb7ef1 Fixed equation solver instructions 2019-03-25 17:08:22 -04:00
WilliamMiceli
2420d52fc3 Added test data for programs to run 2019-03-25 16:00:32 -04:00
WilliamMiceli
5353c8c22e Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/CPU9bits.v
#	lab2CA.srcs/sources_1/new/dataMemory.v
 2019-03-24 19:31:28 -04:00
WilliamMiceli
7490815502 Making fixes to Bubble Sort 2019-03-24 19:27:59 -04:00
Johannes
65b951cf82 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	Bank_behav1.wcfg
#	lab2CA.runs/.jobs/vrs_config_42.xml
#	lab2CA.runs/impl_1/CPU9bits_tb.tcl
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/impl_1/htr.txt
#	lab2CA.runs/impl_1/init_design.pb
#	lab2CA.runs/impl_1/opt_design.pb
#	lab2CA.runs/impl_1/place_design.pb
#	lab2CA.runs/impl_1/vivado.jou
#	lab2CA.runs/impl_1/vivado.pb
#	lab2CA.runs/synth_1/CPU9bits.dcp
#	lab2CA.runs/synth_1/CPU9bits.vds
#	lab2CA.runs/synth_1/CPU9bits_tb.tcl
#	lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
#	lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.runs/synth_1/vivado.jou
#	lab2CA.runs/synth_1/vivado.pb
#	lab2CA.sim/sim_1/behav/xsim/webtalk.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
 2019-03-24 19:02:52 -04:00