William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
176 Commits 1 Branch 0 Tags
847121e65aa9d383db0c644ed556eb897a7f800d
Commit Graph
80 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
WilliamMiceli 847121e65a Not needed 2019-04-10 12:51:47 -04:00
WilliamMiceli f6e59802af Jumping is not working properly 2019-04-10 12:51:30 -04:00
WilliamMiceli eaec5f0883 Vivado stuff 2019-04-10 12:51:15 -04:00
WilliamMiceli e937485bd4 Vivado stuff 2019-04-06 17:44:26 -04:00
WilliamMiceli 93d5687a12 Stopped Vivado from whinning 2019-04-06 17:44:08 -04:00
WilliamMiceli 809bca06bf Vivado metadata 2019-04-06 16:09:17 -04:00
WilliamMiceli 858c1b8e98 Added a lot of points 2019-04-06 16:09:05 -04:00
WilliamMiceli dd7a319e92 Better indentation 2019-04-06 16:08:02 -04:00
WilliamMiceli 3fb02d18e3 Added result, found that waiting 50000 ns is not necessary, as there's a button for it 2019-04-06 16:07:32 -04:00
WilliamMiceli 4aad1aaaf7 Indented better 2019-04-06 16:06:49 -04:00
WilliamMiceli b3e2adb097 Updated simulation 2019-04-06 16:05:47 -04:00
WilliamMiceli c99ae69213 Vivado stuff 2019-04-06 16:05:24 -04:00
WilliamMiceli e79e0cf74d Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 2019-04-06 14:19:45 -04:00
WilliamMiceli 2c2132fb9f Vivado metadata 2019-04-06 14:19:20 -04:00
WilliamMiceli 7715bb2a9c Fixed simulation graphs 2019-04-06 14:19:10 -04:00
WilliamMiceli 31f0d8a9fc Enabled Bubble Sort for testing 2019-04-06 14:18:43 -04:00
WilliamMiceli 3129880d50 Enabled test data for Program 1 2019-04-06 14:18:18 -04:00
WilliamMiceli 7c3f8c6da9 Condensed a little bit. Maybe we can get the first instruction to work 2019-04-06 14:17:47 -04:00
WilliamMiceli f4b2ddebc1 Added back enable signals 2019-04-06 14:17:10 -04:00
WilliamMiceli de8740a231 Vivado runs/sim 2019-04-06 14:16:26 -04:00
WilliamMiceli b4f855c65b Reverting removing the enable signals to test if that is the issue 2019-04-06 14:15:51 -04:00
WilliamMiceli 443d01eba1 Modified sensitivities for result; Vivado metadata 2019-03-30 15:59:43 -04:00
WilliamMiceli ea0111542a Result output of CPU pretty much implemented; not yet tested 2019-03-29 18:16:45 -04:00
WilliamMiceli acf7f9e92b Registers and Banks don't need an enable, should be ignored using MUXes 2019-03-29 18:10:13 -04:00
WilliamMiceli 78f481f724 Vivado stuff 2019-03-29 17:29:24 -04:00
WilliamMiceli 71c6c2ad55 Fixed indentations 2019-03-29 17:28:50 -04:00
WilliamMiceli 2479eefa00 Formatted things to look a little nicer 2019-03-29 17:23:26 -04:00
WilliamMiceli 9fe8656d21 Increased memory size to get rid of unused address ports warning 2019-03-29 17:23:00 -04:00
WilliamMiceli 12700ed019 Simplified and removed latches 2019-03-29 17:22:32 -04:00
WilliamMiceli 9db4c1253b Fixed unconnected wires/ports 2019-03-29 17:22:06 -04:00
WilliamMiceli d8c7031e1b Fixed unconnected wires 2019-03-29 17:21:29 -04:00
WilliamMiceli db8ceeefb5 Now just need to get our programs working 2019-03-29 16:18:19 -04:00
WilliamMiceli 93469aa23f Reordered case statement by opcode and improved comment labels 2019-03-29 16:17:27 -04:00
WilliamMiceli 445f5ce830 Removed CLK, as it is not needed 2019-03-29 16:16:36 -04:00
WilliamMiceli 44c057e40d Simplified testbench a little 2019-03-29 16:16:11 -04:00
WilliamMiceli 20def71bb1 Removed references to CLK, as not needed; simplified testbench a little 2019-03-29 16:15:47 -04:00
WilliamMiceli 352aeefd1b Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM 2019-03-29 16:13:50 -04:00
WilliamMiceli 5bd244f9ba Now Asynchronous and recognized by Vivado as RTL_ROM 2019-03-29 16:13:07 -04:00
WilliamMiceli 5c165d603a Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven 2019-03-29 16:11:52 -04:00
WilliamMiceli 03eb3f3740 Commented out Program 1 test 2019-03-29 14:57:29 -04:00
WilliamMiceli ce86652a00 Aded list of things to fix 2019-03-25 18:04:44 -04:00
WilliamMiceli 97fcfb7ef1 Fixed equation solver instructions 2019-03-25 17:08:22 -04:00
WilliamMiceli 2420d52fc3 Added test data for programs to run 2019-03-25 16:00:32 -04:00
WilliamMiceli 5353c8c22e Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/CPU9bits.v
#	lab2CA.srcs/sources_1/new/dataMemory.v
 2019-03-24 19:31:28 -04:00
WilliamMiceli 7490815502 Making fixes to Bubble Sort 2019-03-24 19:27:59 -04:00
WilliamMiceli 4354aebf8c Merged files 2019-03-24 17:43:32 -04:00
WilliamMiceli 681c506eec Renamed signals on simulation waveforms 2019-03-24 17:42:38 -04:00
WilliamMiceli 1c44d8d964 Added comments to insructions 2019-03-24 17:26:44 -04:00
WilliamMiceli 8e72409386 Added Bubble Sort instructions and initial data memory 2019-03-24 16:54:06 -04:00
WilliamMiceli a978e1fbc6 Revert file 2019-03-24 16:11:31 -04:00
WilliamMiceli f17a0c8954 Replaced missing simulation configuration file 2019-03-24 15:52:26 -04:00
WilliamMiceli ad6765a43a BEQ Opcode fix & other stuffz 2019-03-22 19:54:06 -04:00
WilliamMiceli 934c73e899 Small formatting change 2019-03-16 13:44:44 -04:00
WilliamMiceli b621f5a46b Added sign extension for 3 bits up to 8 bits 2019-03-16 13:23:22 -04:00
WilliamMiceli ef8b9c92e5 Made testbench 2019-03-16 13:02:29 -04:00
WilliamMiceli c988ddb899 Fixed 2 bit module 2019-03-16 13:02:18 -04:00
WilliamMiceli 19ac8e130c Added sign extension for 2 bits into 9 bits, just to test first 2019-03-16 12:55:57 -04:00
WilliamMiceli 047efb7f1f More Vivado stuff 2019-03-12 23:04:47 -04:00
WilliamMiceli 1e0e2bbf31 Jose's awesome way to test zero structurally! 2019-03-12 23:01:18 -04:00
WilliamMiceli 1efd958593 Vivado stuff 2019-03-12 22:56:03 -04:00
WilliamMiceli dbdfc2cfc6 Updated README 2019-03-12 21:53:50 -04:00
WilliamMiceli 76bc5e006e Hopefully this is right. Vivado tells me it's fine, then minutes later not... 2019-03-12 21:21:52 -04:00
WilliamMiceli 4a462752e9 Include NOT in the ALU 2019-03-12 11:23:48 -04:00
WilliamMiceli 97433c3691 Shift right arithmetic implemented into ALU 2019-03-12 11:17:03 -04:00
WilliamMiceli fe1abc30c5 Fixed ALU testbench to 4-bit 2019-03-12 11:12:39 -04:00
WilliamMiceli 9ac8963fb0 ALU now fully has 4-bit opcode 2019-03-12 11:12:21 -04:00
WilliamMiceli 1c5e79c1ec Made 16:1 MUX for ALU's 4-bit opcode 2019-03-12 11:08:22 -04:00
WilliamMiceli 9d759edbec ALU now has 4 bits of it's own opcode 2019-03-12 11:07:50 -04:00
WilliamMiceli 9e9ff7935b Renamed shifting for incoming shift_right_arithmetic 2019-03-12 10:54:45 -04:00
WilliamMiceli f3ea596086 Simplified bitwise OR 2019-03-12 10:48:50 -04:00
WilliamMiceli e01d639fa0 Simplified bitwise NOT 2019-03-12 10:47:25 -04:00
WilliamMiceli a555728a48 Simplified bitwise NOR 2019-03-12 10:46:08 -04:00
WilliamMiceli 9519460187 AND is bitwise, so simplified, removing 1-bit modules 2019-03-12 10:43:16 -04:00
WilliamMiceli 0104b0e689 Possible mistake 2019-02-25 13:30:58 -05:00
WilliamMiceli 39b9ea781e Removed MUX 16:1 as it's not needed 2019-02-25 13:28:28 -05:00
WilliamMiceli 1734d58b47 Adjusted indentation of testbench code 2019-02-25 13:27:22 -05:00
WilliamMiceli 7c83a77713 Activated all testbenches 2019-02-25 12:51:34 -05:00
WilliamMiceli cb30ee7e0a Added list of fixes and things we need to do/implement 2019-02-21 15:11:35 -05:00
WilliamMiceli f9970dec06 Excluded Markdown files 2019-02-21 15:11:10 -05:00
WilliamMiceli 6900e74405 Miscellaneous 2019-02-21 15:09:00 -05:00